[Mesa-dev] [PATCH 3/5] ac/nir: fix atomic compare-and-swap
Samuel Pitoiset
samuel.pitoiset at gmail.com
Wed Apr 11 12:05:06 UTC 2018
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
On 04/11/2018 12:56 PM, Nicolai Hähnle wrote:
> From: Nicolai Hähnle <nicolai.haehnle at amd.com>
>
> The LLVM instruction returns { i32, i1 }, where the i1 indicates success.
> We're only interested in the first part, which is the loaded value.
>
> Fixes dEQP-GLES31.functional.compute.shared_var.atomic.compswap.*
> ---
> src/amd/common/ac_nir_to_llvm.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
> index 7c2bd5c0cca..512d5a8b9ae 100644
> --- a/src/amd/common/ac_nir_to_llvm.c
> +++ b/src/amd/common/ac_nir_to_llvm.c
> @@ -2619,20 +2619,21 @@ static LLVMValueRef visit_var_atomic(struct ac_nir_context *ctx,
> LLVMValueRef src = get_src(ctx, instr->src[src_idx]);
>
> if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap ||
> instr->intrinsic == nir_intrinsic_shared_atomic_comp_swap) {
> LLVMValueRef src1 = get_src(ctx, instr->src[src_idx + 1]);
> result = LLVMBuildAtomicCmpXchg(ctx->ac.builder,
> ptr, src, src1,
> LLVMAtomicOrderingSequentiallyConsistent,
> LLVMAtomicOrderingSequentiallyConsistent,
> false);
> + result = LLVMBuildExtractValue(ctx->ac.builder, result, 0, "");
> } else {
> LLVMAtomicRMWBinOp op;
> switch (instr->intrinsic) {
> case nir_intrinsic_var_atomic_add:
> case nir_intrinsic_shared_atomic_add:
> op = LLVMAtomicRMWBinOpAdd;
> break;
> case nir_intrinsic_var_atomic_umin:
> case nir_intrinsic_shared_atomic_umin:
> op = LLVMAtomicRMWBinOpUMin;
>
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