[Mesa-dev] [1/3] radeonsi: implement mechanism for IBs without partial flushes at the end (v6)

[Benedikt Schemmer]

Hi Marek,

I just tried different combinations: this and with meta

	ctx->flags |= SI_CONTEXT_INV_ICACHE |
	      SI_CONTEXT_INV_SMEM_L1 |
		      SI_CONTEXT_INV_VMEM_L1 |
		      SI_CONTEXT_INV_GLOBAL_L2 |
		      SI_CONTEXT_START_PIPELINE_STATS |
		      SI_CONTEXT_FLUSH_AND_INV_DB |
//		      SI_CONTEXT_FLUSH_AND_INV_DB_META |
		      SI_CONTEXT_FLUSH_AND_INV_CB;

as long as you dont flush db_meta there doesnt seem to be a difference
performancewise and I dont see any visible difference between them at
all cant test this with 32bit applications though

Dirt Rally Benchmark
54/34/71 with meta flush
54/40/74 with db and cb flushes
54/41/73 original

again: gpu limited, all starting with empty shader cache

Cheers,
Benedikt