[Mesa-dev] [RFC PATCH] nir: extend nir_shader_compiler_options with is_scalar

[Jason Ekstrand]

I'm not sure if this should be a NIR compiler option or a PIPE_CAP.  On 
Intel hardware, we have both and we handle it ourselves.

On April 4, 2018 23:04:36 Christian Gmeiner <christian.gmeiner at gmail.com> 
wrote:

> As not every (upcoming) backend compiler is happy with
> nir_lower_xxx_to_scalar lowerings do them only if the backend
> is scalar (and not vec4) based.
>
> Signed-off-by: Christian Gmeiner <christian.gmeiner at gmail.com>
> ---
> src/amd/vulkan/radv_shader.c                | 1 +
> src/broadcom/compiler/nir_to_vir.c          | 1 +
> src/compiler/nir/nir.h                      | 3 +++
> src/gallium/drivers/freedreno/ir3/ir3_nir.c | 1 +
> src/gallium/drivers/radeonsi/si_get.c       | 1 +
> src/gallium/drivers/vc4/vc4_program.c       | 1 +
> src/intel/compiler/brw_compiler.c           | 1 +
> src/mesa/state_tracker/st_glsl_to_nir.cpp   | 8 ++++++--
> 8 files changed, 15 insertions(+), 2 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
> index 171802eede..22f61cb23d 100644
> --- a/src/amd/vulkan/radv_shader.c
> +++ b/src/amd/vulkan/radv_shader.c
> @@ -49,6 +49,7 @@
> #include "util/string_buffer.h"
>
> static const struct nir_shader_compiler_options nir_options = {
> +	.is_scalar = true,
> 	.vertex_id_zero_based = true,
> 	.lower_scmp = true,
> 	.lower_flrp32 = true,
> diff --git a/src/broadcom/compiler/nir_to_vir.c 
> b/src/broadcom/compiler/nir_to_vir.c
> index 595689d244..b4f29554ac 100644
> --- a/src/broadcom/compiler/nir_to_vir.c
> +++ b/src/broadcom/compiler/nir_to_vir.c
> @@ -1876,6 +1876,7 @@ nir_to_vir(struct v3d_compile *c)
> }
>
> const nir_shader_compiler_options v3d_nir_options = {
> +        .is_scalar = true,
>         .lower_all_io_to_temps = true,
>         .lower_extract_byte = true,
>         .lower_extract_word = true,
> diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
> index c676331000..4796e3e88c 100644
> --- a/src/compiler/nir/nir.h
> +++ b/src/compiler/nir/nir.h
> @@ -1883,6 +1883,9 @@ typedef struct nir_shader_compiler_options {
>     */
>    bool native_integers;
>
> +   /* Indicates that the hw makes use of a scalar ISA */
> +   bool is_scalar;
> +
>    /* Indicates that the driver only has zero-based vertex id */
>    bool vertex_id_zero_based;
>
> diff --git a/src/gallium/drivers/freedreno/ir3/ir3_nir.c 
> b/src/gallium/drivers/freedreno/ir3/ir3_nir.c
> index 0b637bb99b..a921c14565 100644
> --- a/src/gallium/drivers/freedreno/ir3/ir3_nir.c
> +++ b/src/gallium/drivers/freedreno/ir3/ir3_nir.c
> @@ -47,6 +47,7 @@ static const nir_shader_compiler_options options = {
> 		.lower_ldexp = true,
> 		.fuse_ffma = true,
> 		.native_integers = true,
> +		.is_scalar = true,
> 		.vertex_id_zero_based = true,
> 		.lower_extract_byte = true,
> 		.lower_extract_word = true,
> diff --git a/src/gallium/drivers/radeonsi/si_get.c 
> b/src/gallium/drivers/radeonsi/si_get.c
> index e9657602f3..621ff86814 100644
> --- a/src/gallium/drivers/radeonsi/si_get.c
> +++ b/src/gallium/drivers/radeonsi/si_get.c
> @@ -510,6 +510,7 @@ static const struct nir_shader_compiler_options 
> nir_options = {
> 	.lower_unpack_unorm_4x8 = true,
> 	.lower_extract_byte = true,
> 	.lower_extract_word = true,
> +	.is_scalar = true,
> 	.max_unroll_iterations = 32,
> 	.native_integers = true,
> };
> diff --git a/src/gallium/drivers/vc4/vc4_program.c 
> b/src/gallium/drivers/vc4/vc4_program.c
> index be80a851d2..1d7d0bdb0a 100644
> --- a/src/gallium/drivers/vc4/vc4_program.c
> +++ b/src/gallium/drivers/vc4/vc4_program.c
> @@ -2191,6 +2191,7 @@ static const nir_shader_compiler_options nir_options = {
>         .lower_ldexp = true,
>         .lower_negate = true,
>         .native_integers = true,
> +        .is_scalar = true,
>         .max_unroll_iterations = 32,
> };
>
> diff --git a/src/intel/compiler/brw_compiler.c 
> b/src/intel/compiler/brw_compiler.c
> index 9340317492..9794362f5d 100644
> --- a/src/intel/compiler/brw_compiler.c
> +++ b/src/intel/compiler/brw_compiler.c
> @@ -57,6 +57,7 @@
>    .lower_unpack_snorm_4x8 = true,                                            \
>    .lower_unpack_unorm_2x16 = true,                                           \
>    .lower_unpack_unorm_4x8 = true,                                            \
> +   .is_scalar = true,                                                      
>    \
>    .vs_inputs_dual_locations = true,                                          \
>    .max_unroll_iterations = 32
>
> diff --git a/src/mesa/state_tracker/st_glsl_to_nir.cpp 
> b/src/mesa/state_tracker/st_glsl_to_nir.cpp
> index 0bd9c4e4e3..9fd64166ae 100644
> --- a/src/mesa/state_tracker/st_glsl_to_nir.cpp
> +++ b/src/mesa/state_tracker/st_glsl_to_nir.cpp
> @@ -262,13 +262,17 @@ st_nir_assign_uniform_locations(struct gl_program *prog,
> static void
> st_nir_opts(nir_shader *nir)
> {
> +   const struct nir_shader_compiler_options *options = nir->options;
>    bool progress;
>    do {
>       progress = false;
>
>       NIR_PASS_V(nir, nir_lower_vars_to_ssa);
> -      NIR_PASS_V(nir, nir_lower_alu_to_scalar);
> -      NIR_PASS_V(nir, nir_lower_phis_to_scalar);
> +
> +      if (options->is_scalar) {
> +         NIR_PASS_V(nir, nir_lower_alu_to_scalar);
> +         NIR_PASS_V(nir, nir_lower_phis_to_scalar);
> +      }
>
>       NIR_PASS_V(nir, nir_lower_64bit_pack);
>       NIR_PASS(progress, nir, nir_copy_prop);
> --
> 2.14.3
>
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