[Mesa-dev] [PATCH 09/17] radeonsi: don't flush HTILE if there is no HTILE clear
Marek Olšák
maraeo at gmail.com
Wed Apr 4 01:59:14 UTC 2018
From: Marek Olšák <marek.olsak at amd.com>
---
src/gallium/drivers/radeonsi/si_clear.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/radeonsi/si_clear.c b/src/gallium/drivers/radeonsi/si_clear.c
index 8aa27b7f405..cbb5e909d3a 100644
--- a/src/gallium/drivers/radeonsi/si_clear.c
+++ b/src/gallium/drivers/radeonsi/si_clear.c
@@ -585,21 +585,22 @@ static void si_clear(struct pipe_context *ctx, unsigned buffers,
* corruption in ARK: Survival Evolved, but that may just be
* a coincidence and the root cause is elsewhere.
*
* The corruption can be fixed by putting the DB flush before
* or after the depth clear. (surprisingly)
*
* https://bugs.freedesktop.org/show_bug.cgi?id=102955 (apitrace)
*
* This hack decreases back-to-back ClearDepth performance.
*/
- if (sctx->screen->clear_db_cache_before_clear) {
+ if ((sctx->db_depth_clear || sctx->db_stencil_clear) &&
+ sctx->screen->clear_db_cache_before_clear) {
sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_DB;
}
}
si_blitter_begin(ctx, SI_CLEAR);
util_blitter_clear(sctx->blitter, fb->width, fb->height,
util_framebuffer_get_num_layers(fb),
buffers, color, depth, stencil);
si_blitter_end(ctx);
--
2.15.1
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