[Mesa-dev] [PATCH] i965/skl: Force the exec size to 8 when initing header for SIMD4x2

[Tapani Pälli]

This fixes 574 failing ES3 conformance tests, nice. Could someone with 
more backend knowledge please review this?

Tested-by: Tapani Pälli <tapani.palli at intel.com>

On 04/24/2015 08:05 AM, Neil Roberts wrote:
> On Gen9+ there needs to be a header when sampling using SIMD4x2. The
> header is set up by copying from the g0 register. Commit 07c571a39f
> tried to fix this mov instruction to always use an exec size of 8
> because previously it was incorrectly using 4. It did this by casting
> the type of the destination register to vec8. This was done because
> there is code in brw_set_dest to guess the exec size based on the
> width of the dest register. However I misunderstood how this works
> because it is actually only used when the width is less than 8. That
> means the patch actually changed it to use the default exec size which
> on SIMD16 would be 16 and the MOV would clobber over the first
> register in the send message. This patch makes it additionally set the
> default exec size to 8. This is similar to how the message is set up
> in fs_generator::generate_tex.
>
> I think this wasn't picked up by any Piglit tests because we don't
> have any fragment shaders that hit this code path so nothing was using
> SIMD16. However the patch caused failures in deqp tests.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90153
> ---
>   src/mesa/drivers/dri/i965/brw_fs_generator.cpp   | 1 +
>   src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 1 +
>   2 files changed, 2 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> index b88dc8e..3bfee7e 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> @@ -1047,6 +1047,7 @@ fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
>
>         brw_push_insn_state(p);
>         brw_set_default_mask_control(p, BRW_MASK_DISABLE);
> +      brw_set_default_exec_size(p, BRW_EXECUTE_8);
>         brw_MOV(p, vec8(src), retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
>         brw_set_default_access_mode(p, BRW_ALIGN_1);
>
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
> index 09a509f..07b008f 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
> @@ -1100,6 +1100,7 @@ vec4_generator::generate_set_simd4x2_header_gen9(vec4_instruction *inst,
>      brw_push_insn_state(p);
>      brw_set_default_mask_control(p, BRW_MASK_DISABLE);
>
> +   brw_set_default_exec_size(p, BRW_EXECUTE_8);
>      brw_MOV(p, vec8(dst), retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
>
>      brw_set_default_access_mode(p, BRW_ALIGN_1);
>