[Mesa-dev] [PATCH 12/21] i965: Define register trait structures.

[Francisco Jerez]

Register traits are a mechanism for back-end agnostic code to query
static properties of the IR the program is being compiled into.  These
properties are fully determined by the flavour of back-end in use,
like the source and destination register types of an instruction, the
number of SIMD slots available per logical thread dispatched to a
single SIMD thread (AKA vector size of the IR), and whether some
specific register type is able to represent vector swizzling and
writemasking.

The trait structures are somewhat unusual in that they are defined
directly inside the register object they describe rather than being a
template parameterized on the register type.  E.g. 't::traits::dst_reg'
queries the matching destination register type for register type 't'.
---
 src/mesa/drivers/dri/i965/brw_ir_fs.h    | 32 ++++++++++++++++
 src/mesa/drivers/dri/i965/brw_ir_svec4.h | 66 ++++++++++++++++++++++++++++++++
 src/mesa/drivers/dri/i965/brw_ir_vec4.h  | 64 +++++++++++++++++++++++++++++++
 3 files changed, 162 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_ir_fs.h b/src/mesa/drivers/dri/i965/brw_ir_fs.h
index b0e07ad..676ed0d 100644
--- a/src/mesa/drivers/dri/i965/brw_ir_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_ir_fs.h
@@ -79,6 +79,38 @@ public:
 
    /** Register region horizontal stride */
    uint8_t stride;
+
+   struct traits {
+      /**
+       * Type used in this IR to represent a source of an instruction.
+       */
+      typedef fs_reg src_reg;
+
+      /**
+       * Type used in this IR to represent the destination of an instruction.
+       */
+      typedef fs_reg dst_reg;
+
+      /**
+       * Base vector size of the IR.  Number of logically independent vector
+       * components available for each channel in a hardware SIMD instruction
+       * or in a dispatch_width-wide register.  This is the number of logical
+       * vector components you get when you allocate a dispatch_width-wide
+       * register, and the number of logical components that offset(reg, 1)
+       * skips over.
+       */
+      static const unsigned chan_size = 1;
+
+      /**
+       * Whether this register type is able to represent vector swizzles.
+       */
+      static const bool allows_swizzle = false;
+
+      /**
+       * Whether this register type is able to represent vector writemasking.
+       */
+      static const bool allows_writemask = false;
+   };
 };
 
 static inline fs_reg
diff --git a/src/mesa/drivers/dri/i965/brw_ir_svec4.h b/src/mesa/drivers/dri/i965/brw_ir_svec4.h
index d1eafdd..90e0305 100644
--- a/src/mesa/drivers/dri/i965/brw_ir_svec4.h
+++ b/src/mesa/drivers/dri/i965/brw_ir_svec4.h
@@ -91,6 +91,39 @@ namespace brw {
       using fs_reg::reladdr;
 
       unsigned swizzle;
+
+      struct traits {
+         /**
+          * Type used in this IR to represent a source of an instruction.
+          */
+         typedef src_svec4 src_reg;
+
+         /**
+          * Type used in this IR to represent the destination of an
+          * instruction.
+          */
+         typedef dst_svec4 dst_reg;
+
+         /**
+          * Base vector size of the IR.  Number of logically independent
+          * vector components available for each channel in a hardware SIMD
+          * instruction or in a dispatch_width-wide register.  This is the
+          * number of logical vector components you get when you allocate a
+          * dispatch_width-wide register, and the number of logical components
+          * that offset(reg, 1) skips over.
+          */
+         static const unsigned chan_size = fs_reg::traits::chan_size;
+
+         /**
+          * Whether this register type is able to represent vector swizzles.
+          */
+         static const bool allows_swizzle = true;
+
+         /**
+          * Whether this register type is able to represent vector writemasking.
+          */
+         static const bool allows_writemask = false;
+      };
    };
 
    /**
@@ -208,6 +241,39 @@ namespace brw {
       using fs_reg::reladdr;
 
       unsigned writemask;
+
+      struct traits {
+         /**
+          * Type used in this IR to represent a source of an instruction.
+          */
+         typedef src_svec4 src_reg;
+
+         /**
+          * Type used in this IR to represent the destination of an
+          * instruction.
+          */
+         typedef dst_svec4 dst_reg;
+
+         /**
+          * Base vector size of the IR.  Number of logically independent
+          * vector components available for each channel in a hardware SIMD
+          * instruction or in a dispatch_width-wide register.  This is the
+          * number of logical vector components you get when you allocate a
+          * dispatch_width-wide register, and the number of logical components
+          * that offset(reg, 1) skips over.
+          */
+         static const unsigned chan_size = fs_reg::traits::chan_size;
+
+         /**
+          * Whether this register type is able to represent vector swizzles.
+          */
+         static const bool allows_swizzle = false;
+
+         /**
+          * Whether this register type is able to represent vector writemasking.
+          */
+         static const bool allows_writemask = true;
+      };
    };
 
    /**
diff --git a/src/mesa/drivers/dri/i965/brw_ir_vec4.h b/src/mesa/drivers/dri/i965/brw_ir_vec4.h
index 9deb694..4a79c57 100644
--- a/src/mesa/drivers/dri/i965/brw_ir_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_ir_vec4.h
@@ -58,6 +58,38 @@ public:
    unsigned swizzle; /**< BRW_SWIZZLE_XYZW macros from brw_reg.h. */
 
    src_reg *reladdr;
+
+   struct traits {
+      /**
+       * Type used in this IR to represent a source of an instruction.
+       */
+      typedef brw::src_reg src_reg;
+
+      /**
+       * Type used in this IR to represent the destination of an instruction.
+       */
+      typedef brw::dst_reg dst_reg;
+
+      /**
+       * Base vector size of the IR.  Number of logically independent vector
+       * components available for each channel in a hardware SIMD instruction
+       * or in a dispatch_width-wide register.  This is the number of logical
+       * vector components you get when you allocate a dispatch_width-wide
+       * register, and the number of logical components that offset(reg, 1)
+       * skips over.
+       */
+      static const unsigned chan_size = 4;
+
+      /**
+       * Whether this register type is able to represent vector swizzles.
+       */
+      static const bool allows_swizzle = true;
+
+      /**
+       * Whether this register type is able to represent vector writemasking.
+       */
+      static const bool allows_writemask = false;
+   };
 };
 
 static inline src_reg
@@ -152,6 +184,38 @@ public:
    unsigned writemask; /**< Bitfield of WRITEMASK_[XYZW] */
 
    src_reg *reladdr;
+
+   struct traits {
+      /**
+       * Type used in this IR to represent a source of an instruction.
+       */
+      typedef brw::src_reg src_reg;
+
+      /**
+       * Type used in this IR to represent the destination of an instruction.
+       */
+      typedef brw::dst_reg dst_reg;
+
+      /**
+       * Base vector size of the IR.  Number of logically independent vector
+       * components available for each channel in a hardware SIMD instruction
+       * or in a dispatch_width-wide register.  This is the number of logical
+       * vector components you get when you allocate a dispatch_width-wide
+       * register, and the number of logical components that offset(reg, 1)
+       * skips over.
+       */
+      static const unsigned chan_size = 4;
+
+      /**
+       * Whether this register type is able to represent vector swizzles.
+       */
+      static const bool allows_swizzle = false;
+
+      /**
+       * Whether this register type is able to represent vector writemasking.
+       */
+      static const bool allows_writemask = true;
+   };
 };
 
 static inline dst_reg
-- 
2.3.5