[Mesa-dev] [PATCH 6/7] i965: ensure execution of fragment shader when fragment shader has atomic buffer access

[kevin.rogovin at intel.com]

From: Kevin Rogovin <kevin.rogovin at intel.com>

Ensure that the GPU spawns the fragment shader thread for those
fragment shaders with atomic buffer access. 

---
 src/mesa/drivers/dri/i965/gen7_wm_state.c | 7 +++++++
 src/mesa/drivers/dri/i965/gen8_ps_state.c | 4 ++++
 2 files changed, 11 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c b/src/mesa/drivers/dri/i965/gen7_wm_state.c
index 82e116c..fa04221 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_state.c
@@ -77,6 +77,13 @@ upload_wm_state(struct brw_context *brw)
       dw1 |= GEN7_WM_KILL_ENABLE;
    }
 
+   /* pixel shader must run if it has side-effects
+    */
+   if (brw->ctx.Shader._CurrentFragmentProgram!=NULL &&
+       brw->ctx.Shader._CurrentFragmentProgram->NumAtomicBuffers > 0) {
+     dw1 |= GEN7_WM_DISPATCH_ENABLE;
+   }
+
    /* _NEW_BUFFERS | _NEW_COLOR */
    if (brw_color_buffer_write_enabled(brw) || writes_depth ||
        dw1 & GEN7_WM_KILL_ENABLE) {
diff --git a/src/mesa/drivers/dri/i965/gen8_ps_state.c b/src/mesa/drivers/dri/i965/gen8_ps_state.c
index 5f39e12..614bc9b 100644
--- a/src/mesa/drivers/dri/i965/gen8_ps_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_ps_state.c
@@ -62,6 +62,10 @@ upload_ps_extra(struct brw_context *brw)
    if (prog_data->uses_omask)
       dw1 |= GEN8_PSX_OMASK_TO_RENDER_TARGET;
 
+   if (brw->ctx.Shader._CurrentFragmentProgram!=NULL &&
+       brw->ctx.Shader._CurrentFragmentProgram->NumAtomicBuffers > 0)
+      dw1 |= GEN8_PSX_SHADER_HAS_UAV;
+
    BEGIN_BATCH(2);
    OUT_BATCH(_3DSTATE_PS_EXTRA << 16 | (2 - 2));
    OUT_BATCH(dw1);
-- 
1.9.1