[Mesa-dev] [PATCH V2 05/22] i965: Pass miptree pointer as function parameter in intel_vertical_texture_alignment_unit

[Pohjolainen, Topi]

On Fri, Apr 17, 2015 at 04:51:26PM -0700, Anuj Phogat wrote:
> Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
> ---
>  src/mesa/drivers/dri/i965/brw_tex_layout.c | 18 ++++++++----------
>  1 file changed, 8 insertions(+), 10 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c
> index e74e263..68c6634 100644
> --- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
> +++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
> @@ -90,7 +90,7 @@ intel_horizontal_texture_alignment_unit(struct brw_context *brw,
>  
>  static unsigned int
>  intel_vertical_texture_alignment_unit(struct brw_context *brw,
> -                                      mesa_format format, bool multisampled)
> +                                      struct intel_mipmap_tree *mt)

const (only used for reading).

>  {
>     /**
>      * From the "Alignment Unit Size" section of various specs, namely:
> @@ -115,10 +115,10 @@ intel_vertical_texture_alignment_unit(struct brw_context *brw,
>      * Where "*" means either VALIGN_2 or VALIGN_4 depending on the setting of
>      * the SURFACE_STATE "Surface Vertical Alignment" field.
>      */
> -   if (_mesa_is_format_compressed(format))
> +   if (_mesa_is_format_compressed(mt->format))
>        return 4;
>  
> -   if (format == MESA_FORMAT_S_UINT8)
> +   if (mt->format == MESA_FORMAT_S_UINT8)
>        return brw->gen >= 7 ? 8 : 4;
>  
>     /* Broadwell only supports VALIGN of 4, 8, and 16.  The BSpec says 4
> @@ -127,10 +127,10 @@ intel_vertical_texture_alignment_unit(struct brw_context *brw,
>     if (brw->gen >= 8)
>        return 4;
>  
> -   if (multisampled)
> +   if (mt->num_samples > 1)
>        return 4;
>  
> -   GLenum base_format = _mesa_get_format_base_format(format);
> +   GLenum base_format = _mesa_get_format_base_format(mt->format);
>  
>     if (brw->gen >= 6 &&
>         (base_format == GL_DEPTH_COMPONENT ||
> @@ -151,7 +151,7 @@ intel_vertical_texture_alignment_unit(struct brw_context *brw,
>         *
>         *     VALIGN_4 is not supported for surface format R32G32B32_FLOAT.
>         */
> -      if (base_format == GL_YCBCR_MESA || format == MESA_FORMAT_RGB_FLOAT32)
> +      if (base_format == GL_YCBCR_MESA || mt->format == MESA_FORMAT_RGB_FLOAT32)
>           return 2;
>  
>        return 4;
> @@ -538,7 +538,6 @@ brw_miptree_layout(struct brw_context *brw,
>                     enum intel_miptree_tiling_mode requested,
>                     struct intel_mipmap_tree *mt)
>  {
> -   bool multisampled = mt->num_samples > 1;
>     bool gen6_hiz_or_stencil = false;
>  
>     if (brw->gen == 6 && mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
> @@ -570,9 +569,8 @@ brw_miptree_layout(struct brw_context *brw,
>           mt->align_h = 32;
>        }
>     } else {
> -      mt->align_w = intel_horizontal_texture_alignment_unit(brw, mt);
> -      mt->align_h =
> -         intel_vertical_texture_alignment_unit(brw, mt->format, multisampled);
> +      mt->align_w =  intel_horizontal_texture_alignment_unit(brw, mt);

extra space

Otherwise:

Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>

> +      mt->align_h = intel_vertical_texture_alignment_unit(brw, mt);
>     }
>  
>     intel_miptree_total_width_height(brw, mt);
> -- 
> 2.3.4
> 
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