[Mesa-dev] [PATCH 02/14] i965/blorp/gen6: Support for loading glsl-based fragment shaders

[Topi Pohjolainen]

Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
---
 src/mesa/drivers/dri/i965/brw_blorp.h    |  1 +
 src/mesa/drivers/dri/i965/gen6_blorp.cpp | 74 ++++++++++++++++++++++++++++++++
 2 files changed, 75 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h b/src/mesa/drivers/dri/i965/brw_blorp.h
index aa83c66..9fd4193 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -407,6 +407,7 @@ public:
 
    virtual void gen6_emit_wm_constants(struct brw_context *brw);
 
+   virtual void gen6_emit_wm_config(struct brw_context *brw) const;
    virtual void gen7_emit_wm_config(struct brw_context *brw) const;
 
    virtual void gen6_emit_multisample_state(struct brw_context *brw) const;
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index 39d32df..7ba414e 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -34,6 +34,8 @@
 #include "brw_blorp.h"
 #include "gen6_blorp.h"
 
+#include "program/program.h"
+
 /**
  * \name Constants for BLORP VBO
  * \{
@@ -719,6 +721,67 @@ gen6_blorp_emit_wm_config(struct brw_context *brw,
    ADVANCE_BATCH();
 }
 
+static void
+gen6_meta_emit_wm_config(struct brw_context *brw,
+                         const struct gl_fragment_program *fp,
+                         const struct brw_wm_prog_data *prog_data,
+                         const struct brw_stage_state *stage_state,
+                         bool multisampled_fbo)
+{
+   uint32_t dw2, dw4, dw5, dw6, ksp0, ksp2;
+
+   dw2 = dw4 = dw5 = dw6 = ksp0 = ksp2 = 0;
+
+   dw5 |= GEN6_WM_LINE_AA_WIDTH_1_0;
+   dw5 |= GEN6_WM_LINE_END_CAP_AA_WIDTH_0_5;
+   dw5 |= (brw->max_wm_threads - 1) << GEN6_WM_MAX_THREADS_SHIFT;
+   dw6 |= prog_data->num_varying_inputs << GEN6_WM_NUM_SF_OUTPUTS_SHIFT;
+
+   dw6 |= prog_data->barycentric_interp_modes <<
+          GEN6_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT;
+
+   dw2 |= (ALIGN(stage_state->sampler_count, 4) / 4) <<
+          GEN6_WM_SAMPLER_COUNT_SHIFT;
+
+   dw2 |= (prog_data->base.binding_table.size_bytes / 4) <<
+          GEN6_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT;
+
+   if (prog_data->uses_kill | prog_data->uses_omask)
+      dw5 |= GEN6_WM_KILL_ENABLE;
+
+   dw5 |= GEN6_WM_DISPATCH_ENABLE; /* We are rendering */
+
+   if (prog_data->uses_omask)
+      dw5 |= GEN6_WM_OMASK_TO_RENDER_TARGET;
+
+   if (multisampled_fbo)
+      dw6 |= GEN6_WM_MSDISPMODE_PERPIXEL;
+   else
+      dw6 |= GEN6_WM_MSDISPMODE_PERSAMPLE;
+
+   dw6 |= GEN6_WM_MSRAST_OFF_PIXEL;
+
+   if (prog_data->uses_pos_offset)
+      dw6 |= GEN6_WM_POSOFFSET_SAMPLE;
+   else
+      dw6 |= GEN6_WM_POSOFFSET_NONE;
+
+   const int min_inv_per_frag = 1;
+   gen6_wm_state_set_programs(prog_data, stage_state, min_inv_per_frag,
+                              &ksp0, &ksp2, &dw4, &dw5, &dw6);
+
+   BEGIN_BATCH(9);
+   OUT_BATCH(_3DSTATE_WM << 16 | (9 - 2));
+   OUT_BATCH(ksp0);
+   OUT_BATCH(dw2);
+   OUT_BATCH(0); /* No scratch needed */
+   OUT_BATCH(dw4);
+   OUT_BATCH(dw5);
+   OUT_BATCH(dw6);
+   OUT_BATCH(0); /* No other programs */
+   OUT_BATCH(ksp2);
+   ADVANCE_BATCH();
+}
 
 static void
 gen6_blorp_emit_constant_ps(struct brw_context *brw,
@@ -1094,6 +1157,17 @@ brw_meta_fs_params::gen6_emit_wm_constants(struct brw_context *brw)
 }
 
 void
+brw_meta_fs_params::gen6_emit_wm_config(struct brw_context *brw) const
+{
+   gen6_upload_constant_state(brw, wm_prog_data, &wm_stage_state);
+
+   const bool multisampled_fbo = dst_num_samples > 1;
+   gen6_meta_emit_wm_config(brw, fp, wm_prog_data, &wm_stage_state,
+                            multisampled_fbo);
+   gen6_blorp_emit_binding_table_pointers(brw, wm_stage_state.bind_bo_offset);
+}
+
+void
 brw_meta_fs_params::gen6_emit_multisample_state(struct brw_context *brw) const
 {
    const unsigned sample_mask =
-- 
1.9.3