[Mesa-dev] [PATCH 06/16] i965/blorp: Prepare for attributes other than render position

[Topi Pohjolainen]

Note that the magic number of one in gen7 logic is replaced by
BRW_SF_URB_ENTRY_READ_OFFSET ( == 1 also) for clarity.

On gen6 the change from zero to one (BRW_SF_URB_ENTRY_READ_OFFSET)
has no effect for native blorp as blorp doesn't use any
additional attributes. In fact, regular pipeline setup always
uses BRW_SF_URB_ENTRY_READ_OFFSET even when there are no additional
attributes. Hence the change makes the two (blorp and regular)
consistent.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
---
 src/mesa/drivers/dri/i965/brw_blorp.cpp  | 5 +++--
 src/mesa/drivers/dri/i965/brw_blorp.h    | 3 ++-
 src/mesa/drivers/dri/i965/gen6_blorp.cpp | 5 +++--
 src/mesa/drivers/dri/i965/gen7_blorp.cpp | 6 ++++--
 4 files changed, 12 insertions(+), 7 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index b0de55d..0c0cd2b 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -155,14 +155,15 @@ brw_blorp_surface_info::compute_tile_offsets(uint32_t *tile_x,
 }
 
 
-brw_blorp_params::brw_blorp_params()
+brw_blorp_params::brw_blorp_params(unsigned num_varyings)
    : x0(0),
      y0(0),
      x1(0),
      y1(0),
      depth_format(0),
      hiz_op(GEN6_HIZ_OP_NONE),
-     use_wm_prog(false)
+     use_wm_prog(false),
+     num_varyings(num_varyings)
 {
    color_write_disable[0] = false;
    color_write_disable[1] = false;
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h b/src/mesa/drivers/dri/i965/brw_blorp.h
index 5889f3e..a84b664 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -211,7 +211,7 @@ struct brw_blorp_prog_data
 class brw_blorp_params
 {
 public:
-   brw_blorp_params();
+   explicit brw_blorp_params(unsigned num_varyings = 0);
 
    virtual uint32_t get_wm_prog(struct brw_context *brw,
                                 brw_blorp_prog_data **prog_data) const = 0;
@@ -228,6 +228,7 @@ public:
    bool use_wm_prog;
    brw_blorp_wm_push_constants wm_push_consts;
    bool color_write_disable[4];
+   const unsigned num_varyings;
 };
 
 
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index 9b54b93..2954750 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -634,9 +634,10 @@ gen6_blorp_emit_sf_config(struct brw_context *brw,
 {
    BEGIN_BATCH(20);
    OUT_BATCH(_3DSTATE_SF << 16 | (20 - 2));
-   OUT_BATCH((1 - 1) << GEN6_SF_NUM_OUTPUTS_SHIFT | /* only position */
+   OUT_BATCH(params->num_varyings << GEN6_SF_NUM_OUTPUTS_SHIFT |
              1 << GEN6_SF_URB_ENTRY_READ_LENGTH_SHIFT |
-             0 << GEN6_SF_URB_ENTRY_READ_OFFSET_SHIFT);
+             BRW_SF_URB_ENTRY_READ_OFFSET <<
+                GEN6_SF_URB_ENTRY_READ_OFFSET_SHIFT);
    OUT_BATCH(0); /* dw2 */
    OUT_BATCH(params->dst.num_samples > 1 ? GEN6_SF_MSRAST_ON_PATTERN : 0);
    for (int i = 0; i < 16; ++i)
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index 12f515d..3065a4c 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -415,9 +415,11 @@ gen7_blorp_emit_sf_config(struct brw_context *brw,
    {
       BEGIN_BATCH(14);
       OUT_BATCH(_3DSTATE_SBE << 16 | (14 - 2));
-      OUT_BATCH((1 - 1) << GEN7_SBE_NUM_OUTPUTS_SHIFT | /* only position */
+      OUT_BATCH(GEN7_SBE_SWIZZLE_ENABLE |
+                params->num_varyings << GEN7_SBE_NUM_OUTPUTS_SHIFT |
                 1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT |
-                0 << GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT);
+                BRW_SF_URB_ENTRY_READ_OFFSET <<
+                   GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT);
       for (int i = 0; i < 12; ++i)
          OUT_BATCH(0);
       ADVANCE_BATCH();
-- 
1.9.3