[Mesa-dev] [PATCH 01/10] i965/fs: Ensure delta_x/y are even-aligned registers on Gen6.

[Jason Ekstrand]

On Fri, Apr 17, 2015 at 11:40 AM, Matt Turner <mattst88 at gmail.com> wrote:
> On Fri, Apr 17, 2015 at 11:13 AM, Jason Ekstrand <jason at jlekstrand.net> wrote:
>> On Tue, Apr 14, 2015 at 4:15 PM, Matt Turner <mattst88 at gmail.com> wrote:
>>> The BSpec says this applies to Gen6 as well.
>>> ---
>>>  src/mesa/drivers/dri/i965/brw_fs_generator.cpp    | 2 +-
>>>  src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 4 ++--
>>>  2 files changed, 3 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
>>> index 2743297..78925d7 100644
>>> --- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
>>> +++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
>>> @@ -428,7 +428,7 @@ fs_generator::generate_linterp(fs_inst *inst,
>>>
>>>     if (brw->has_pln &&
>>>         delta_y.nr == delta_x.nr + 1 &&
>>> -       (brw->gen >= 6 || (delta_x.nr & 1) == 0)) {
>>> +       (brw->gen >= 7 || (delta_x.nr & 1) == 0)) {
>>>        brw_PLN(p, dst, interp, delta_x);
>>
>> I think this hunk is premature.  If not, it at least doesn't match the
>> commit message. :-)
>
> I don't think so. The bit I'm changing was (gen >= 6 || delta_x is
> even), and so since the BSpec says Gen4-6 need delta_x to be even, the
> early-out needs to be gen >= 7.

Right... That clears it up.