[Mesa-dev] [PATCH 01/10] i965/fs: Ensure delta_x/y are even-aligned registers on Gen6.

[Jason Ekstrand]

On Tue, Apr 14, 2015 at 4:15 PM, Matt Turner <mattst88 at gmail.com> wrote:
> The BSpec says this applies to Gen6 as well.
> ---
>  src/mesa/drivers/dri/i965/brw_fs_generator.cpp    | 2 +-
>  src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 4 ++--
>  2 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> index 2743297..78925d7 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> @@ -428,7 +428,7 @@ fs_generator::generate_linterp(fs_inst *inst,
>
>     if (brw->has_pln &&
>         delta_y.nr == delta_x.nr + 1 &&
> -       (brw->gen >= 6 || (delta_x.nr & 1) == 0)) {
> +       (brw->gen >= 7 || (delta_x.nr & 1) == 0)) {
>        brw_PLN(p, dst, interp, delta_x);

I think this hunk is premature.  If not, it at least doesn't match the
commit message. :-)

>     } else {
>        brw_LINE(p, brw_null_reg(), interp, delta_x);
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
> index 2dfafdf..2a4054a 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
> @@ -245,9 +245,9 @@ brw_alloc_reg_set(struct intel_screen *screen, int reg_width)
>     assert(reg == ra_reg_count);
>
>     /* Add a special class for aligned pairs, which we'll put delta_x/y
> -    * in on gen5 so that we can do PLN.
> +    * in on Gen <= 6 so that we can do PLN.
>      */
> -   if (devinfo->has_pln && reg_width == 1 && devinfo->gen < 6) {
> +   if (devinfo->has_pln && reg_width == 1 && devinfo->gen <= 6) {
>        aligned_pairs_class = ra_alloc_reg_class(regs);
>
>        for (int i = 0; i < pairs_reg_count; i++) {
> --
> 2.0.5
>
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