[Mesa-dev] [PATCH 2/3] gallium/ttn: add support for temp arrays

[Rob Clark]

On Fri, Apr 10, 2015 at 2:13 AM, Eric Anholt <eric at anholt.net> wrote:
> Rob Clark <robdclark at gmail.com> writes:
>> From: Rob Clark <robclark at freedesktop.org>
>>
>> Since the rest of NIR really would rather have these as variables rather
>> than registers, create a nir_variable per array.  But rather than
>> completely re-arrange ttn to be variable based rather than register
>> based, keep the registers.  In the cases where there is a matching var
>> for the reg, ttn_emit_instruction will append the appropriate intrinsic
>> to get things back from the shadow reg into the variable.
>>
>> NOTE: this doesn't quite handle TEMP[ADDR[]] when the DCL doesn't give
>> an array id.  But those just kinda suck, and should really go away.
>> AFAICT we don't get those from glsl.  Might be an issue for some other
>> state tracker.
>>
>> v2: rework to use load_var/store_var with deref chains
>> v3: create new "burner" reg for temporarily holding the (potentially
>> writemask'd) dest after each instruction; add load_var to initialize
>> temporary dest in case not all components are overwritten
>> +/* generate either a constant or indirect deref chain for accessing an
>> + * array variable.
>> + */
>> +static nir_deref_var *
>> +ttn_array_deref(struct ttn_compile *c, nir_variable *var, unsigned offset,
>> +                struct tgsi_ind_register *indirect)
>> +{
>> +   nir_builder *b = &c->build;
>> +   nir_deref_var *deref = nir_deref_var_create(b->shader, var);
>> +   nir_deref_array *arr = nir_deref_array_create(b->shader);
>> +
>> +   arr->base_offset = offset;
>> +   arr->deref.type = glsl_get_array_element(var->type);
>> +
>> +   if (indirect) {
>> +      arr->deref_array_type = nir_deref_array_type_indirect;
>> +      arr->indirect = nir_src_for_reg(c->addr_reg);
>
> I just noticed.  What i should have said here is "this should be
> ttn_src_for_indirect(c, indirect)" instead.

*ahh*.. ok, so that already does the mov to vec1, which sounds like it
should address my concern about a vec4 addr register..  let's give
that a try..

BR,
-R

>> +   } else {
>> +      arr->deref_array_type = nir_deref_array_type_direct;
>> +   }
>> +
>> +   deref->deref.child = &arr->deref;
>> +
>> +   return deref;
>> +}