[Mesa-dev] [PATCH] i965: Fix depth field setting in surface state for raw buffer on Gen7/8

[Zhenyu Wang]

On 2015.04.07 09:18:08 -0700, Kristian Høgsberg wrote:
> On Mon, Apr 6, 2015 at 10:51 PM, Zhenyu Wang <zhenyuw at linux.intel.com> wrote:
> > On Gen7/8 for RAW surface format, the depth field (surf[3]) in surface
> > state means [30:21] bits of number of entries which is different from
> > other surface format which uses [26:21] bits field.
> >
> > Signed-off-by: Zhenyu Wang <zhenyuw at linux.intel.com>
> 
> Is there  a bugzilla that this fixes we can link from the commit
> message? Either way, this looks good.
> 
> Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
> 

Not yet, as I have another client to use raw surface, so better to
fix this with spec.

thanks

-- 
Open Source Technology Center, Intel ltd.

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