[PATCH 4/5] arm64: dst: qcom: sm8450: switch to usb3/dp combo phy

[Neil Armstrong]

On 06/02/2023 12:03, Konrad Dybcio wrote:
> subject: s/dst/dts here and in 5/5
> 
> On 6.02.2023 11:17, Neil Armstrong wrote:
>> The QMP PHY is a USB3/DP combo phy, switch to the newly
>> documented bindings and register the clocks to the GCC
>> and DISPCC controllers.
>>
>> Signed-off-by: Neil Armstrong <neil.armstrong at linaro.org>
>> ---
>>   arch/arm64/boot/dts/qcom/sm8450.dtsi | 38 +++++++++++++-----------------------
>>   1 file changed, 14 insertions(+), 24 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
>> index d66dcd8fe61f..757b7c56d5f5 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
>> @@ -748,7 +748,7 @@ gcc: clock-controller at 100000 {
>>   				 <&ufs_mem_phy_lanes 0>,
>>   				 <&ufs_mem_phy_lanes 1>,
>>   				 <&ufs_mem_phy_lanes 2>,
>> -				 <0>;
>> +				 <&usb_1_qmpphy 0>;
>>   			clock-names = "bi_tcxo",
>>   				      "sleep_clk",
>>   				      "pcie_0_pipe_clk",
>> @@ -2038,37 +2038,27 @@ usb_1_hsphy: phy at 88e3000 {
>>   			resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
>>   		};
>>   
>> -		usb_1_qmpphy: phy-wrapper at 88e9000 {
>> -			compatible = "qcom,sm8450-qmp-usb3-phy";
>> -			reg = <0 0x088e9000 0 0x200>,
>> -			      <0 0x088e8000 0 0x20>;
>> -			status = "disabled";
>> +		usb_1_qmpphy: phy at 88e8000 {
>> +			compatible = "qcom,sm8450-qmp-usb3-dp-phy";
>> +			reg = <0 0x088e8000 0 0x4000>;
> 
>>   			#address-cells = <2>;
>>   			#size-cells = <2>;
>>   			ranges;
> These can go since you're removing the subnode, I think..

Indeed will remove

>>   
>>   			clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
>>   				 <&rpmhcc RPMH_CXO_CLK>,
>> -				 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
>> -			clock-names = "aux", "ref_clk_src", "com_aux";
>> +				 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
>> +				 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
>> +			clock-names = "aux", "ref", "com_aux", "usb3_pipe";
>>   
>>   			resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
>>   				 <&gcc GCC_USB3_PHY_PRIM_BCR>;
>>   			reset-names = "phy", "common";
>>   
>> -			usb_1_ssphy: phy at 88e9200 {
>> -				reg = <0 0x088e9200 0 0x200>,
>> -				      <0 0x088e9400 0 0x200>,
>> -				      <0 0x088e9c00 0 0x400>,
>> -				      <0 0x088e9600 0 0x200>,
>> -				      <0 0x088e9800 0 0x200>,
>> -				      <0 0x088e9a00 0 0x100>;
>> -				#phy-cells = <0>;
>> -				#clock-cells = <0>;
>> -				clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
>> -				clock-names = "pipe0";
>> -				clock-output-names = "usb3_phy_pipe_clk_src";
>> -			};
>> +			#clock-cells = <1>;
>> +			#phy-cells = <1>;
>> +
>> +			status = "disabled";
>>   		};
>>   
>>   		remoteproc_slpi: remoteproc at 2400000 {
>> @@ -2976,8 +2966,8 @@ dispcc: clock-controller at af00000 {
>>   				 <&mdss_dsi0_phy 1>,
>>   				 <&mdss_dsi1_phy 0>,
>>   				 <&mdss_dsi1_phy 1>,
>> -				 <0>, /* dp0 */
>> -				 <0>,
>> +				 <&usb_1_qmpphy 0>,
>> +				 <&usb_1_qmpphy 1>,
>>   				 <0>, /* dp1 */
>>   				 <0>,
>>   				 <0>, /* dp2 */
>> @@ -4157,7 +4147,7 @@ usb_1_dwc3: usb at a600000 {
>>   				iommus = <&apps_smmu 0x0 0x0>;
>>   				snps,dis_u2_susphy_quirk;
>>   				snps,dis_enblslpm_quirk;
>> -				phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
>> +				phys = <&usb_1_hsphy>, <&usb_1_qmpphy 0>;
>>   				phy-names = "usb2-phy", "usb3-phy";
> BTW msm-5.10 marks the dwc3 subdevice dma-coherent, maybe we should too?

Probably, not sure it's related to this patchset

Neil

> 
> Konrad
>>   			};
>>   		};
>>