diff --git a/src/legacy_output.c b/src/legacy_output.c
index f9b0dff..e7d6e32 100644
--- a/src/legacy_output.c
+++ b/src/legacy_output.c
@@ -153,6 +153,15 @@ RADEONRestoreRMXRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore)
 
 }
 
+static void
+RADEONSelDiv0(ScrnInfoPtr pScrn)
+{
+    RADEONInfoPtr  info       = RADEONPTR(pScrn);
+    unsigned char *RADEONMMIO = info->MMIO;
+
+    OUTREG(RADEON_CLOCK_CNTL_INDEX, 0);
+}
+
 /* Write LVDS registers */
 void
 RADEONRestoreLVDSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore)
@@ -163,12 +172,7 @@ RADEONRestoreLVDSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore)
     if (info->IsMobility) {
 	OUTREG(RADEON_LVDS_GEN_CNTL,  restore->lvds_gen_cntl);
 	/*OUTREG(RADEON_LVDS_PLL_CNTL,  restore->lvds_pll_cntl);*/
-
-	if (info->ChipFamily == CHIP_FAMILY_RV410) {
-	    OUTREG(RADEON_CLOCK_CNTL_INDEX, 0);
-	}
     }
-
 }
 
 void
@@ -1419,6 +1423,8 @@ legacy_output_mode_set(xf86OutputPtr output, DisplayModePtr mode,
     case MT_LCD:
 	ErrorF("restore LVDS\n");
 	RADEONRestoreLVDSRegisters(pScrn, info->ModeReg);
+	if ((radeon_crtc->crtc_id == 0) && (info->ChipFamily == CHIP_FAMILY_RV410))
+	    RADEONSelDiv0(pScrn);
 	break;
     case MT_DFP:
 	if (radeon_output->TMDSType == TMDS_INT) {
@@ -1447,6 +1453,8 @@ legacy_output_mode_set(xf86OutputPtr output, DisplayModePtr mode,
 	    } else {
 		RADEONRestoreFP2Registers(pScrn, info->ModeReg);
 		RADEONRestoreDVOChip(pScrn, output);
+		if ((radeon_crtc->crtc_id == 0) && info->IsIGP)
+		    RADEONSelDiv0(pScrn);
 	    }
 	}
 	break;