[PATCH 1/2] Use/define RADEON_GPU_PAGE_SIZE instead of sprinkling 4096 everywhere.
Jerome Glisse
jglisse at redhat.com
Thu Feb 25 01:53:32 PST 2010
On Wed, Feb 24, 2010 at 10:46:27PM -0500, Matt Turner wrote:
> Also, define RADEON_BUFFER_ALIGN in terms of it, and replace some
> RADEON_ALIGN(x, RADEON_BUFFER_ALIGN) with RADEON_ALIGN(x,
> RADEON_GPU_PAGE_SIZE) since this is really what was intended.
>
Patch looks good
Reviewed-by: Jerome Glisse <jglisse at redhat.com>
> CC: Jerome Glisse <jglisse at redhat.com>
> CC: Alex Deucher <alexdeucher at gmail.com>
> CC: Dave Airlie <airlied at redhat.com>
> Signed-off-by: Matt Turner <mattst88 at gmail.com>
> ---
> src/radeon.h | 3 ++-
> src/radeon_accel.c | 27 ++++++++++++---------------
> src/radeon_crtc.c | 4 ++--
> src/radeon_driver.c | 8 ++++----
> src/radeon_exa.c | 6 +++---
> src/radeon_exa_funcs.c | 2 +-
> src/radeon_kms.c | 5 ++---
> src/radeon_legacy_memory.c | 2 +-
> 8 files changed, 27 insertions(+), 30 deletions(-)
>
> diff --git a/src/radeon.h b/src/radeon.h
> index c0b5d7a..c1feb03 100644
> --- a/src/radeon.h
> +++ b/src/radeon.h
> @@ -234,7 +234,8 @@ typedef enum {
> #define RADEON_VSYNC_TIMEOUT 20000 /* Maximum wait for VSYNC (in usecs) */
>
> /* Buffer are aligned on 4096 byte boundaries */
> -#define RADEON_BUFFER_ALIGN 0x00000fff
> +#define RADEON_GPU_PAGE_SIZE 4096
> +#define RADEON_BUFFER_ALIGN (RADEON_GPU_PAGE_SIZE - 1)
> #define RADEON_VBIOS_SIZE 0x00010000
> #define RADEON_USE_RMX 0x80000000 /* mode flag for using RMX
> * Need to comfirm this is not used
> diff --git a/src/radeon_accel.c b/src/radeon_accel.c
> index f0d94c3..9bf8f3c 100644
> --- a/src/radeon_accel.c
> +++ b/src/radeon_accel.c
> @@ -1157,11 +1157,11 @@ RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen)
> * Might need that for non-XF86DRI too?
> */
> if (info->allowColorTiling) {
> - bufferSize = (((pScrn->virtualY + 15) & ~15) * width_bytes
> - + RADEON_BUFFER_ALIGN) & ~RADEON_BUFFER_ALIGN;
> + bufferSize = RADEON_ALIGN(((pScrn->virtualY + 15) & ~15) * width_bytes,
> + RADEON_GPU_PAGE_SIZE);
> } else {
> - bufferSize = (pScrn->virtualY * width_bytes
> - + RADEON_BUFFER_ALIGN) & ~RADEON_BUFFER_ALIGN;
> + bufferSize = RADEON_ALIGN(pScrn->virtualY * width_bytes,
> + RADEON_GPU_PAGE_SIZE);
> }
>
> /* Due to tiling, the Z buffer pitch must be a multiple of 32 pixels,
> @@ -1169,8 +1169,8 @@ RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen)
> * but not necessarily otherwise, and its height a multiple of 16 lines.
> */
> info->dri->depthPitch = (pScrn->displayWidth + 31) & ~31;
> - depthSize = ((((pScrn->virtualY + 15) & ~15) * info->dri->depthPitch
> - * depthCpp + RADEON_BUFFER_ALIGN) & ~RADEON_BUFFER_ALIGN);
> + depthSize = RADEON_ALIGN(((pScrn->virtualY + 15) & ~15) * info->dri->depthPitch
> + * depthCpp, RADEON_GPU_PAGE_SIZE);
>
> xf86DrvMsg(pScrn->scrnIndex, X_INFO,
> "Using %d MB GART aperture\n", info->dri->gartSize);
> @@ -1277,25 +1277,22 @@ RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen)
> }
> else {
> /* Reserve space for textures */
> - info->dri->textureOffset = ((info->FbMapSize - info->dri->textureSize +
> - RADEON_BUFFER_ALIGN) &
> - ~(uint32_t)RADEON_BUFFER_ALIGN);
> + info->dri->textureOffset = RADEON_ALIGN(info->FbMapSize - info->dri->textureSize,
> + RADEON_GPU_PAGE_SIZE);
> }
>
> /* Reserve space for the shared depth
> * buffer.
> */
> - info->dri->depthOffset = ((info->dri->textureOffset - depthSize +
> - RADEON_BUFFER_ALIGN) &
> - ~(uint32_t)RADEON_BUFFER_ALIGN);
> + info->dri->depthOffset = RADEON_ALIGN(info->dri->textureOffset - depthSize,
> + RADEON_GPU_PAGE_SIZE);
>
> /* Reserve space for the shared back buffer */
> if (info->dri->noBackBuffer) {
> info->dri->backOffset = info->dri->depthOffset;
> } else {
> - info->dri->backOffset = ((info->dri->depthOffset - bufferSize +
> - RADEON_BUFFER_ALIGN) &
> - ~(uint32_t)RADEON_BUFFER_ALIGN);
> + info->dri->backOffset = RADEON_ALIGN(info->dri->depthOffset - bufferSize,
> + RADEON_GPU_PAGE_SIZE);
> }
>
> info->dri->backY = info->dri->backOffset / width_bytes;
> diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
> index 79ea4df..0635c91 100644
> --- a/src/radeon_crtc.c
> +++ b/src/radeon_crtc.c
> @@ -646,7 +646,7 @@ radeon_crtc_shadow_allocate (xf86CrtcPtr crtc, int width, int height)
> RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
> unsigned long rotate_pitch;
> unsigned long rotate_offset;
> - int align = 4096, size;
> + int size;
> int cpp = pScrn->bitsPerPixel / 8;
>
> /* No rotation without accel */
> @@ -666,7 +666,7 @@ radeon_crtc_shadow_allocate (xf86CrtcPtr crtc, int width, int height)
> * allocate offscreen memory and fake up a pixmap header for it.
> */
> rotate_offset = radeon_legacy_allocate_memory(pScrn, &radeon_crtc->crtc_rotate_mem,
> - size, align, RADEON_GEM_DOMAIN_VRAM);
> + size, RADEON_GPU_PAGE_SIZE, RADEON_GEM_DOMAIN_VRAM);
> if (rotate_offset == 0)
> return NULL;
>
> diff --git a/src/radeon_driver.c b/src/radeon_driver.c
> index 9a4cb9a..b65e3f8 100644
> --- a/src/radeon_driver.c
> +++ b/src/radeon_driver.c
> @@ -4286,8 +4286,8 @@ void RADEONChangeSurfaces(ScrnInfoPtr pScrn)
> int cpp = info->CurrentLayout.pixel_bytes;
> /* depth/front/back pitch must be identical (and the same as displayWidth) */
> int width_bytes = pScrn->displayWidth * cpp;
> - int bufferSize = ((((pScrn->virtualY + 15) & ~15) * width_bytes
> - + RADEON_BUFFER_ALIGN) & ~RADEON_BUFFER_ALIGN);
> + int bufferSize = RADEON_ALIGN(((pScrn->virtualY + 15) & ~15) * width_bytes,
> + RADEON_GPU_PAGE_SIZE);
> unsigned int color_pattern, swap_pattern;
>
> if (!info->allowColorTiling)
> @@ -4319,8 +4319,8 @@ void RADEONChangeSurfaces(ScrnInfoPtr pScrn)
> int retvalue;
> int depthCpp = (info->dri->depthBits - 8) / 4;
> int depth_width_bytes = pScrn->displayWidth * depthCpp;
> - int depthBufferSize = ((((pScrn->virtualY + 15) & ~15) * depth_width_bytes
> - + RADEON_BUFFER_ALIGN) & ~RADEON_BUFFER_ALIGN);
> + int depthBufferSize = RADEON_ALIGN(((pScrn->virtualY + 15) & ~15) * depth_width_bytes,
> + RADEON_GPU_PAGE_SIZE);
> unsigned int depth_pattern;
>
> drmsurffree.address = info->dri->frontOffset;
> diff --git a/src/radeon_exa.c b/src/radeon_exa.c
> index f8b0cc9..63ded94 100644
> --- a/src/radeon_exa.c
> +++ b/src/radeon_exa.c
> @@ -232,7 +232,7 @@ static Bool RADEONPrepareAccess_BE(PixmapPtr pPix, int index)
> * surface. We need to align the size first
> */
> size = exaGetPixmapSize(pPix);
> - size = (size + RADEON_BUFFER_ALIGN) & ~(RADEON_BUFFER_ALIGN);
> + size = RADEON_ALIGN(size, RADEON_GPU_PAGE_SIZE);
>
> /* Set surface to tiling disabled with appropriate swapper */
> switch (bpp) {
> @@ -635,7 +635,7 @@ Bool RADEONSetupMemEXA (ScreenPtr pScreen)
> * offscreen locations does.
> */
> info->dri->backPitch = pScrn->displayWidth;
> - next = RADEON_ALIGN(info->accel_state->exa->offScreenBase, RADEON_BUFFER_ALIGN);
> + next = RADEON_ALIGN(info->accel_state->exa->offScreenBase, RADEON_GPU_PAGE_SIZE);
> if (!info->dri->noBackBuffer &&
> next + screen_size <= info->accel_state->exa->memorySize)
> {
> @@ -651,7 +651,7 @@ Bool RADEONSetupMemEXA (ScreenPtr pScreen)
> */
> info->dri->depthPitch = RADEON_ALIGN(pScrn->displayWidth, 32);
> depth_size = RADEON_ALIGN(pScrn->virtualY, 16) * info->dri->depthPitch * depthCpp;
> - next = RADEON_ALIGN(info->accel_state->exa->offScreenBase, RADEON_BUFFER_ALIGN);
> + next = RADEON_ALIGN(info->accel_state->exa->offScreenBase, RADEON_GPU_PAGE_SIZE);
> if (next + depth_size <= info->accel_state->exa->memorySize)
> {
> info->dri->depthOffset = next;
> diff --git a/src/radeon_exa_funcs.c b/src/radeon_exa_funcs.c
> index 5806d3b..91a1c75 100644
> --- a/src/radeon_exa_funcs.c
> +++ b/src/radeon_exa_funcs.c
> @@ -820,7 +820,7 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen)
> /* The 2D engine supports overlapping memory areas */
> info->accel_state->exa->flags |= EXA_SUPPORTS_OFFSCREEN_OVERLAPS;
> #endif
> - info->accel_state->exa->pixmapOffsetAlign = RADEON_BUFFER_ALIGN + 1;
> + info->accel_state->exa->pixmapOffsetAlign = RADEON_GPU_PAGE_SIZE;
> info->accel_state->exa->pixmapPitchAlign = 64;
>
> #ifdef EXA_HANDLES_PIXMAPS
> diff --git a/src/radeon_kms.c b/src/radeon_kms.c
> index b4e1759..1585f49 100644
> --- a/src/radeon_kms.c
> +++ b/src/radeon_kms.c
> @@ -908,7 +908,6 @@ static Bool radeon_setup_kernel_mem(ScreenPtr pScreen)
> int screen_size;
> int stride = pScrn->displayWidth * cpp;
> int total_size_bytes = 0, remain_size_bytes;
> - int pagesize = 4096;
>
> if (info->accel_state->exa != NULL) {
> xf86DrvMsg(pScreen->myNum, X_ERROR, "Memory map already initialized\n");
> @@ -925,7 +924,7 @@ static Bool radeon_setup_kernel_mem(ScreenPtr pScreen)
> int cursor_size = 64 * 4 * 64;
> int c;
>
> - cursor_size = RADEON_ALIGN(cursor_size, pagesize);
> + cursor_size = RADEON_ALIGN(cursor_size, RADEON_GPU_PAGE_SIZE);
> for (c = 0; c < xf86_config->num_crtc; c++) {
> /* cursor objects */
> if (info->cursor_bo[c] == NULL) {
> @@ -951,7 +950,7 @@ static Bool radeon_setup_kernel_mem(ScreenPtr pScreen)
> }
> }
>
> - screen_size = RADEON_ALIGN(screen_size, pagesize);
> + screen_size = RADEON_ALIGN(screen_size, RADEON_GPU_PAGE_SIZE);
> /* keep area front front buffer - but don't allocate it yet */
> total_size_bytes += screen_size;
>
> diff --git a/src/radeon_legacy_memory.c b/src/radeon_legacy_memory.c
> index bdf8ca2..3e75291 100644
> --- a/src/radeon_legacy_memory.c
> +++ b/src/radeon_legacy_memory.c
> @@ -26,7 +26,7 @@ radeon_legacy_allocate_memory(ScrnInfoPtr pScrn,
> if (info->cs) {
> struct radeon_bo *video_bo;
>
> - video_bo = radeon_bo_open(info->bufmgr, 0, size, 4096, domain, 0);
> + video_bo = radeon_bo_open(info->bufmgr, 0, size, RADEON_GPU_PAGE_SIZE, domain, 0);
>
> *mem_struct = video_bo;
>
> --
> 1.6.4.4
>
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