[PATCH 1/1] Uncomment PCI access functions inside server
Tiago Vignatti
vignatti at freedesktop.org
Tue Apr 28 18:33:08 PDT 2009
This reintroduces secondary cards initialization.
We're currently living in a completely mess regarding the resources
access control. Some accesses are done by libpciaccess, other by Xorg
and other simply don't exist yet (e.g. arbitration of legacy VGA). We
can discuss about a beautiful redesign later. In this moment I just want
to put back the multiple card, multiple head functionality. The first
step is to reintroduce secondary cards initialization. I'll keep the work.
PS.: AFAIK the currently implementation of int10's x86emu backend is not
working to POST secondary cards (BUG). I POSTed using vm86 instead.
Signed-off-by: Tiago Vignatti <vignatti at freedesktop.org>
---
hw/xfree86/common/xf86pciBus.c | 33 ---------------------------------
1 files changed, 0 insertions(+), 33 deletions(-)
diff --git a/hw/xfree86/common/xf86pciBus.c b/hw/xfree86/common/xf86pciBus.c
index 854a837..c467f75 100644
--- a/hw/xfree86/common/xf86pciBus.c
+++ b/hw/xfree86/common/xf86pciBus.c
@@ -115,25 +115,21 @@ xf86FormatPciBusNumber(int busnum, char *buffer)
static void
pciIoAccessEnable(void* arg)
{
-#if 0
#ifdef DEBUG
ErrorF("pciIoAccessEnable: 0x%05lx\n", *(PCITAG *)arg);
#endif
pArg->ctrl |= SETBITS | PCI_CMD_MASTER_ENABLE;
pci_device_cfg_write_u32(pArg->dev, pArg->ctrl, PCI_CMD_STAT_REG);
-#endif
}
static void
pciIoAccessDisable(void* arg)
{
-#if 0
#ifdef DEBUG
ErrorF("pciIoAccessDisable: 0x%05lx\n", *(PCITAG *)arg);
#endif
pArg->ctrl &= ~SETBITS;
pci_device_cfg_write_u32(pArg->dev, pArg->ctrl, PCI_CMD_STAT_REG);
-#endif
}
#undef SETBITS
@@ -141,25 +137,21 @@ pciIoAccessDisable(void* arg)
static void
pciIo_MemAccessEnable(void* arg)
{
-#if 0
#ifdef DEBUG
ErrorF("pciIo_MemAccessEnable: 0x%05lx\n", *(PCITAG *)arg);
#endif
pArg->ctrl |= SETBITS | PCI_CMD_MASTER_ENABLE;
pci_device_cfg_write_u32(pArg->dev, pArg->ctrl, PCI_CMD_STAT_REG);
-#endif
}
static void
pciIo_MemAccessDisable(void* arg)
{
-#if 0
#ifdef DEBUG
ErrorF("pciIo_MemAccessDisable: 0x%05lx\n", *(PCITAG *)arg);
#endif
pArg->ctrl &= ~SETBITS;
pci_device_cfg_write_u32(pArg->dev, pArg->ctrl, PCI_CMD_STAT_REG);
-#endif
}
#undef SETBITS
@@ -167,25 +159,21 @@ pciIo_MemAccessDisable(void* arg)
static void
pciMemAccessEnable(void* arg)
{
-#if 0
#ifdef DEBUG
ErrorF("pciMemAccessEnable: 0x%05lx\n", *(PCITAG *)arg);
#endif
pArg->ctrl |= SETBITS | PCI_CMD_MASTER_ENABLE;
pci_device_cfg_write_u32(pArg->dev, pArg->ctrl, PCI_CMD_STAT_REG);
-#endif
}
static void
pciMemAccessDisable(void* arg)
{
-#if 0
#ifdef DEBUG
ErrorF("pciMemAccessDisable: 0x%05lx\n", *(PCITAG *)arg);
#endif
pArg->ctrl &= ~SETBITS;
pci_device_cfg_write_u32(pArg->dev, pArg->ctrl, PCI_CMD_STAT_REG);
-#endif
}
#undef SETBITS
#undef pArg
@@ -196,7 +184,6 @@ pciMemAccessDisable(void* arg)
static void
pciBusAccessEnable(BusAccPtr ptr)
{
-#if 0
struct pci_device * const dev = ptr->busdep.pci.dev;
uint16_t ctrl;
@@ -209,14 +196,12 @@ pciBusAccessEnable(BusAccPtr ptr)
~(PCI_PCI_BRIDGE_MASTER_ABORT_EN | PCI_PCI_BRIDGE_SECONDARY_RESET);
pci_device_cfg_write_u16(dev, ctrl, PCI_PCI_BRIDGE_CONTROL_REG);
}
-#endif
}
/* move to OS layer */
static void
pciBusAccessDisable(BusAccPtr ptr)
{
-#if 0
struct pci_device * const dev = ptr->busdep.pci.dev;
uint16_t ctrl;
@@ -228,7 +213,6 @@ pciBusAccessDisable(BusAccPtr ptr)
ctrl &= ~(MASKBITS | PCI_PCI_BRIDGE_SECONDARY_RESET);
pci_device_cfg_write_u16(dev, ctrl, PCI_PCI_BRIDGE_CONTROL_REG);
}
-#endif
}
#undef MASKBITS
@@ -265,7 +249,6 @@ pciSetBusAccess(BusAccPtr ptr)
static void
savePciState( struct pci_device * dev, pciSavePtr ptr )
{
-#if 0
int i;
pci_device_cfg_read_u32( dev, & ptr->command, PCI_CMD_STAT_REG );
@@ -276,11 +259,9 @@ savePciState( struct pci_device * dev, pciSavePtr ptr )
}
pci_device_cfg_read_u32( dev, & ptr->biosBase, PCI_CMD_BIOS_REG );
-#endif
}
/* move to OS layer */
-#if 0
static void
restorePciState( struct pci_device * dev, pciSavePtr ptr)
{
@@ -299,13 +280,11 @@ restorePciState( struct pci_device * dev,
pciSavePtr ptr)
pci_device_cfg_write_u32(dev, ptr->command, PCI_CMD_STAT_REG);
}
-#endif
/* move to OS layer */
static void
savePciBusState(BusAccPtr ptr)
{
-#if 0
struct pci_device * const dev = ptr->busdep.pci.dev;
uint16_t temp;
@@ -317,7 +296,6 @@ savePciBusState(BusAccPtr ptr)
temp = ptr->busdep.pci.save.control & ~PCI_PCI_BRIDGE_MASTER_ABORT_EN;
pci_device_cfg_read_u16( dev, & temp, PCI_PCI_BRIDGE_CONTROL_REG );
}
-#endif
}
/* move to OS layer */
@@ -325,7 +303,6 @@ savePciBusState(BusAccPtr ptr)
static void
restorePciBusState(BusAccPtr ptr)
{
-#if 0
struct pci_device * const dev = ptr->busdep.pci.dev;
uint16_t ctrl;
@@ -337,11 +314,9 @@ restorePciBusState(BusAccPtr ptr)
ctrl |= ptr->busdep.pci.save.control & MASKBITS;
pci_device_cfg_write_u16(dev, ctrl, PCI_PCI_BRIDGE_CONTROL_REG);
}
-#endif
}
#undef MASKBITS
-
/*
* xf86Bus.c interface
*/
@@ -630,7 +605,6 @@ PciBusStateEnter(void)
void
PciStateLeave(void)
{
-#if 0
unsigned i;
if (xf86PciVideoInfo == NULL)
@@ -644,13 +618,11 @@ PciStateLeave(void)
restorePciState(paccp->arg.dev, &paccp->save);
}
}
-#endif
}
void
PciBusStateLeave(void)
{
-#if 0
BusAccPtr pbap = xf86BusAccInfo;
while (pbap) {
@@ -658,13 +630,11 @@ PciBusStateLeave(void)
pbap->restore_f(pbap);
pbap = pbap->next;
}
-#endif
}
void
DisablePciAccess(void)
{
-#if 0
unsigned i;
if (xf86PciVideoInfo == NULL)
@@ -677,13 +647,11 @@ DisablePciAccess(void)
pciIo_MemAccessDisable(paccp->io_memAccess.arg);
}
}
-#endif
}
void
DisablePciBusAccess(void)
{
-#if 0
BusAccPtr pbap = xf86BusAccInfo;
while (pbap) {
@@ -693,7 +661,6 @@ DisablePciBusAccess(void)
pbap->primary->current = NULL;
pbap = pbap->next;
}
-#endif
}
/*
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