xf86-video-intel: src/sna/gen4_render.c src/sna/gen5_render.c
Chris Wilson
ickle at kemper.freedesktop.org
Wed Feb 22 13:05:12 PST 2012
src/sna/gen4_render.c | 55 ++++++++++++++++++++++++--------------------------
src/sna/gen5_render.c | 10 +++------
2 files changed, 31 insertions(+), 34 deletions(-)
New commits:
commit 510767e213c2f44563f5c438ad1234113567be90
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Wed Feb 22 18:33:09 2012 +0000
sna/gen4: Fix vertex flushing across batch flushing
Due to the w/a for its buggy shaders, gen4 is significantly different
that backporting the simple patch from gen5 was prone to failure. We
need to check that the vertices have not already been flushed prior to
flushing again.
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
diff --git a/src/sna/gen4_render.c b/src/sna/gen4_render.c
index f6a47a0..4bc2938 100644
--- a/src/sna/gen4_render.c
+++ b/src/sna/gen4_render.c
@@ -351,8 +351,7 @@ static void gen4_magic_ca_pass(struct sna *sna,
static void gen4_vertex_flush(struct sna *sna)
{
- if (sna->render_state.gen4.vertex_offset == 0)
- return;
+ assert(sna->render_state.gen4.vertex_offset);
DBG(("%s[%x] = %d\n", __FUNCTION__,
4*sna->render_state.gen4.vertex_offset,
@@ -1182,8 +1181,10 @@ inline static int gen4_get_rectangles(struct sna *sna,
return want;
flush:
- gen4_vertex_flush(sna);
- gen4_magic_ca_pass(sna, op);
+ if (sna->render_state.gen4.vertex_offset) {
+ gen4_vertex_flush(sna);
+ gen4_magic_ca_pass(sna, op);
+ }
return 0;
}
@@ -1202,14 +1203,6 @@ static uint32_t *gen4_composite_get_binding_table(struct sna *sna,
}
static void
-gen4_emit_sip(struct sna *sna)
-{
- /* Set system instruction pointer */
- OUT_BATCH(GEN4_STATE_SIP | 0);
- OUT_BATCH(0);
-}
-
-static void
gen4_emit_urb(struct sna *sna)
{
int urb_vs_start, urb_vs_size;
@@ -1282,7 +1275,6 @@ gen4_emit_invariant(struct sna *sna)
else
OUT_BATCH(GEN4_PIPELINE_SELECT | PIPELINE_SELECT_3D);
- gen4_emit_sip(sna);
gen4_emit_state_base_address(sna);
sna->render_state.gen4.needs_invariant = FALSE;
@@ -1803,7 +1795,8 @@ gen4_render_video(struct sna *sna,
}
priv->clear = false;
- gen4_vertex_flush(sna);
+ if (sna->render_state.gen4.vertex_offset)
+ gen4_vertex_flush(sna);
return TRUE;
}
@@ -1920,8 +1913,10 @@ gen4_render_composite_done(struct sna *sna,
{
DBG(("%s()\n", __FUNCTION__));
- gen4_vertex_flush(sna);
- gen4_magic_ca_pass(sna, op);
+ if (sna->render_state.gen4.vertex_offset) {
+ gen4_vertex_flush(sna);
+ gen4_magic_ca_pass(sna, op);
+ }
if (op->mask.bo)
kgem_bo_destroy(&sna->kgem, op->mask.bo);
@@ -2240,7 +2235,7 @@ gen4_render_composite(struct sna *sna,
if (too_large(tmp->dst.width, tmp->dst.height) &&
!sna_render_composite_redirect(sna, tmp,
dst_x, dst_y, width, height))
- return FALSE;
+ return FALSE;
switch (gen4_composite_picture(sna, src, &tmp->src,
src_x, src_y,
@@ -2600,7 +2595,8 @@ gen4_render_copy_blt(struct sna *sna,
static void
gen4_render_copy_done(struct sna *sna, const struct sna_copy_op *op)
{
- gen4_vertex_flush(sna);
+ if (sna->render_state.gen4.vertex_offset)
+ gen4_vertex_flush(sna);
}
static Bool
@@ -2765,7 +2761,9 @@ gen4_render_fill_boxes(struct sna *sna,
return FALSE;
}
- if (prefer_blt(sna) || too_large(dst->drawable.width, dst->drawable.height)) {
+ if (prefer_blt(sna) ||
+ too_large(dst->drawable.width, dst->drawable.height) ||
+ !gen4_check_dst_format(format)) {
uint8_t alu = -1;
if (op == PictOpClear || (op == PictOpOutReverse && color->alpha >= 0xff00))
@@ -2806,11 +2804,11 @@ gen4_render_fill_boxes(struct sna *sna,
if (op == PictOpClear)
pixel = 0;
else if (!sna_get_pixel_from_rgba(&pixel,
- color->red,
- color->green,
- color->blue,
- color->alpha,
- PICT_a8r8g8b8))
+ color->red,
+ color->green,
+ color->blue,
+ color->alpha,
+ PICT_a8r8g8b8))
return FALSE;
DBG(("%s(%08x x %d)\n", __FUNCTION__, pixel, n));
@@ -2888,7 +2886,8 @@ gen4_render_fill_op_boxes(struct sna *sna,
static void
gen4_render_fill_op_done(struct sna *sna, const struct sna_fill_op *op)
{
- gen4_vertex_flush(sna);
+ if (sna->render_state.gen4.vertex_offset)
+ gen4_vertex_flush(sna);
kgem_bo_destroy(&sna->kgem, op->base.src.bo);
}
@@ -2949,7 +2948,7 @@ gen4_render_fill(struct sna *sna, uint8_t alu,
op->base.u.gen4.wm_kernel = WM_KERNEL;
op->base.u.gen4.ve_id = 1;
- if (!kgem_check_bo(&sna->kgem, dst_bo, NULL)) {
+ if (!kgem_check_bo(&sna->kgem, dst_bo, NULL)) {
kgem_submit(&sna->kgem);
assert(kgem_check_bo(&sna->kgem, dst_bo, NULL));
}
@@ -3048,7 +3047,8 @@ gen4_render_fill_one(struct sna *sna, PixmapPtr dst, struct kgem_bo *bo,
gen4_render_fill_rectangle(sna, &tmp, x1, y1, x2 - x1, y2 - y1);
- gen4_vertex_flush(sna);
+ if (sna->render_state.gen4.vertex_offset)
+ gen4_vertex_flush(sna);
kgem_bo_destroy(&sna->kgem, tmp.src.bo);
return TRUE;
@@ -3113,7 +3113,6 @@ static uint32_t gen4_create_sf_state(struct sna_static_stream *stream,
sf_state->thread4.max_threads = SF_MAX_THREADS - 1;
sf_state->thread4.urb_entry_allocation_size = URB_SF_ENTRY_SIZE - 1;
sf_state->thread4.nr_urb_entries = URB_SF_ENTRIES;
- sf_state->thread4.stats_enable = 1;
sf_state->sf5.viewport_transform = FALSE; /* skip viewport */
sf_state->sf6.cull_mode = GEN4_CULLMODE_NONE;
sf_state->sf6.scissor = 0;
diff --git a/src/sna/gen5_render.c b/src/sna/gen5_render.c
index 64be24b..ac55b09 100644
--- a/src/sna/gen5_render.c
+++ b/src/sna/gen5_render.c
@@ -1549,7 +1549,6 @@ static void gen5_bind_surfaces(struct sna *sna,
gen5_emit_state(sna, op, offset);
}
-
fastcall static void
gen5_render_composite_blt(struct sna *sna,
const struct sna_composite_op *op,
@@ -2273,11 +2272,10 @@ gen5_render_composite(struct sna *sna,
sna_render_reduce_damage(tmp, dst_x, dst_y, width, height);
- if (too_large(tmp->dst.width, tmp->dst.height)) {
- if (!sna_render_composite_redirect(sna, tmp,
- dst_x, dst_y, width, height))
- return FALSE;
- }
+ if (too_large(tmp->dst.width, tmp->dst.height) &&
+ !sna_render_composite_redirect(sna, tmp,
+ dst_x, dst_y, width, height))
+ return FALSE;
DBG(("%s: preparing source\n", __FUNCTION__));
switch (gen5_composite_picture(sna, src, &tmp->src,
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