xf86-video-ati: Branch 'master'

[Jerome Glisse]

 src/radeon_exa.c |    7 +++++++
 1 file changed, 7 insertions(+)

New commits:
commit d282719a9c2fb0ee32830aa75b8dfbb9392954ed
Author: Jerome Glisse <jglisse at redhat.com>
Date:   Wed Apr 4 17:08:30 2012 -0400

    r6xx-r9xx: force 1D tiling for buffer with height < 64
    
    Due to some old kernel issue, height is 8 aligned insided the ddx
    For buffer with height btw 57 & 63 this lead ddx to believe it can
    allocate a 2D tiled surface while mesa will not align height and
    will assume 1D tiled leading to disagreement and rendering issue.
    This patch force buffer with height < 64 to be 1D tiled.
    
    Signed-off-by: Jerome Glisse <jglisse at redhat.com>

diff --git a/src/radeon_exa.c b/src/radeon_exa.c
index 99a5806..270dad4 100644
--- a/src/radeon_exa.c
+++ b/src/radeon_exa.c
@@ -511,6 +511,13 @@ void *RADEONEXACreatePixmap2(ScreenPtr pScreen, int width, int height,
 			surface.last_level = 0;
 			surface.bpe = cpp;
 			surface.nsamples = 1;
+			if (height < 64) {
+				/* disable 2d tiling for small surface to work around
+				 * the fact that ddx align height to 8 pixel for old
+				 * obscure reason i can't remember
+				 */
+				tiling &= ~RADEON_TILING_MACRO;
+			}
 			surface.flags = RADEON_SURF_SCANOUT;
 			surface.flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
 			surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR, MODE);