xf86-video-ati: Branch 'master' - 2 commits
Alex Deucher
agd5f at kemper.freedesktop.org
Tue Apr 13 08:12:11 PDT 2010
src/atombios_crtc.c | 22 +++++++++++++++++++++-
src/atombios_output.c | 8 ++++++--
src/legacy_crtc.c | 28 ++++++++++++++++++++++------
src/radeon.h | 2 +-
src/radeon_crtc.c | 37 +++++++++++++++----------------------
src/radeon_probe.h | 6 ++++++
6 files changed, 71 insertions(+), 32 deletions(-)
New commits:
commit 22a46dddd375b2b9399e12fdf168fa5292ff17a4
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Tue Apr 13 11:08:59 2010 -0400
radeon: add support for pll algo selection
tv-out on atom systems is very particular about it's
dividers. force it to use the old algo.
Should fix fdo bug 27593.
diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c
index 1d86643..6f083b4 100644
--- a/src/atombios_crtc.c
+++ b/src/atombios_crtc.c
@@ -458,6 +458,19 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode)
unsigned char *space;
memset(&spc_param, 0, sizeof(spc_param));
+
+ if (IS_AVIVO_VARIANT) {
+ if (xf86ReturnOptValBool(info->Options, OPTION_NEW_PLL, TRUE))
+ radeon_crtc->pll_algo = RADEON_PLL_NEW;
+ else
+ radeon_crtc->pll_algo = RADEON_PLL_OLD;
+ } else {
+ if (xf86ReturnOptValBool(info->Options, OPTION_NEW_PLL, FALSE))
+ radeon_crtc->pll_algo = RADEON_PLL_NEW;
+ else
+ radeon_crtc->pll_algo = RADEON_PLL_OLD;
+ }
+
if (IS_AVIVO_VARIANT) {
if ((info->ChipFamily == CHIP_FAMILY_RS600) ||
(info->ChipFamily == CHIP_FAMILY_RS690) ||
@@ -471,6 +484,7 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode)
for (i = 0; i < xf86_config->num_output; i++) {
xf86OutputPtr output = xf86_config->output[i];
if (output->crtc == crtc) {
+ radeon_output = output->driver_private;
radeon_encoder = radeon_get_encoder(output);
/* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
/* AdjustDisplayPll handles this on DCE3.x */
@@ -478,6 +492,11 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode)
(radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1) &&
!IS_DCE3_VARIANT)
sclock *= 2;
+ if (radeon_output->active_device &
+ (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)) {
+ pll_flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
+ radeon_crtc->pll_algo = RADEON_PLL_OLD;
+ }
}
}
@@ -614,7 +633,8 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode)
}
}
- RADEONComputePLL(pScrn, &info->pll, sclock, &temp, &fb_div, &frac_fb_div, &ref_div, &post_div, pll_flags);
+ RADEONComputePLL(crtc, &info->pll, sclock, &temp,
+ &fb_div, &frac_fb_div, &ref_div, &post_div, pll_flags);
sclock = temp; /* 10 khz */
xf86DrvMsg(crtc->scrn->scrnIndex, X_INFO,
diff --git a/src/legacy_crtc.c b/src/legacy_crtc.c
index e4c1f04..0beb54d 100644
--- a/src/legacy_crtc.c
+++ b/src/legacy_crtc.c
@@ -1184,10 +1184,12 @@ RADEONInitCrtc2Registers(xf86CrtcPtr crtc, RADEONSavePtr save,
/* Define PLL registers for requested video mode */
static void
-RADEONInitPLLRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save,
+RADEONInitPLLRegisters(xf86CrtcPtr crtc, RADEONSavePtr save,
RADEONPLLPtr pll, DisplayModePtr mode,
int flags)
{
+ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
+ ScrnInfoPtr pScrn = crtc->scrn;
RADEONInfoPtr info = RADEONPTR(pScrn);
uint32_t feedback_div = 0;
uint32_t frac_fb_div = 0;
@@ -1223,7 +1225,13 @@ RADEONInitPLLRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save,
return;
}
- RADEONComputePLL(pScrn, pll, mode->Clock, &freq, &feedback_div, &frac_fb_div, &reference_div, &post_divider, flags);
+ if (xf86ReturnOptValBool(info->Options, OPTION_NEW_PLL, FALSE))
+ radeon_crtc->pll_algo = RADEON_PLL_NEW;
+ else
+ radeon_crtc->pll_algo = RADEON_PLL_OLD;
+
+ RADEONComputePLL(crtc, pll, mode->Clock, &freq,
+ &feedback_div, &frac_fb_div, &reference_div, &post_divider, flags);
for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
if (post_div->divider == post_divider)
@@ -1266,10 +1274,12 @@ RADEONInitPLLRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save,
/* Define PLL2 registers for requested video mode */
static void
-RADEONInitPLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save,
+RADEONInitPLL2Registers(xf86CrtcPtr crtc, RADEONSavePtr save,
RADEONPLLPtr pll, DisplayModePtr mode,
int flags)
{
+ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
+ ScrnInfoPtr pScrn = crtc->scrn;
RADEONInfoPtr info = RADEONPTR(pScrn);
uint32_t feedback_div = 0;
uint32_t frac_fb_div = 0;
@@ -1303,7 +1313,13 @@ RADEONInitPLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save,
return;
}
- RADEONComputePLL(pScrn, pll, mode->Clock, &freq, &feedback_div, &frac_fb_div, &reference_div, &post_divider, flags);
+ if (xf86ReturnOptValBool(info->Options, OPTION_NEW_PLL, FALSE))
+ radeon_crtc->pll_algo = RADEON_PLL_NEW;
+ else
+ radeon_crtc->pll_algo = RADEON_PLL_OLD;
+
+ RADEONComputePLL(crtc, pll, mode->Clock, &freq,
+ &feedback_div, &frac_fb_div, &reference_div, &post_divider, flags);
for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
if (post_div->divider == post_divider)
@@ -1795,7 +1811,7 @@ legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
dot_clock = adjusted_mode->Clock / 1000.0;
if (dot_clock) {
ErrorF("init pll1\n");
- RADEONInitPLLRegisters(pScrn, info->ModeReg, &info->pll, adjusted_mode, pll_flags);
+ RADEONInitPLLRegisters(crtc, info->ModeReg, &info->pll, adjusted_mode, pll_flags);
} else {
info->ModeReg->ppll_ref_div = info->SavedReg->ppll_ref_div;
info->ModeReg->ppll_div_3 = info->SavedReg->ppll_div_3;
@@ -1809,7 +1825,7 @@ legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
dot_clock = adjusted_mode->Clock / 1000.0;
if (dot_clock) {
ErrorF("init pll2\n");
- RADEONInitPLL2Registers(pScrn, info->ModeReg, &info->pll, adjusted_mode, pll_flags);
+ RADEONInitPLL2Registers(crtc, info->ModeReg, &info->pll, adjusted_mode, pll_flags);
}
break;
}
diff --git a/src/radeon.h b/src/radeon.h
index 88f1516..388422a 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -1176,7 +1176,7 @@ extern void radeon_crtc_load_lut(xf86CrtcPtr crtc);
extern void radeon_crtc_modeset_ioctl(xf86CrtcPtr crtc, Bool post);
extern Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask);
extern void RADEONBlank(ScrnInfoPtr pScrn);
-extern void RADEONComputePLL(ScrnInfoPtr pScrn,
+extern void RADEONComputePLL(xf86CrtcPtr crtc,
RADEONPLLPtr pll, unsigned long freq,
uint32_t *chosen_dot_clock_freq,
uint32_t *chosen_feedback_div,
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index 0b071b8..a4a3302 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -447,7 +447,7 @@ done:
}
void
-RADEONComputePLL(ScrnInfoPtr pScrn,
+RADEONComputePLL(xf86CrtcPtr crtc,
RADEONPLLPtr pll,
unsigned long freq,
uint32_t *chosen_dot_clock_freq,
@@ -457,28 +457,21 @@ RADEONComputePLL(ScrnInfoPtr pScrn,
uint32_t *chosen_post_div,
int flags)
{
- RADEONInfoPtr info = RADEONPTR(pScrn);
+ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
- if (IS_AVIVO_VARIANT) {
- if (xf86ReturnOptValBool(info->Options, OPTION_NEW_PLL, TRUE)) {
- /* disable frac fb dividers */
- flags &= ~RADEON_PLL_USE_FRAC_FB_DIV;
- RADEONComputePLL_new(pll, freq, chosen_dot_clock_freq,
- chosen_feedback_div, chosen_frac_feedback_div,
- chosen_reference_div, chosen_post_div, flags);
- } else
- RADEONComputePLL_old(pll, freq, chosen_dot_clock_freq,
- chosen_feedback_div, chosen_frac_feedback_div,
- chosen_reference_div, chosen_post_div, flags);
- } else {
- if (xf86ReturnOptValBool(info->Options, OPTION_NEW_PLL, FALSE))
- RADEONComputePLL_new(pll, freq, chosen_dot_clock_freq,
- chosen_feedback_div, chosen_frac_feedback_div,
- chosen_reference_div, chosen_post_div, flags);
- else
- RADEONComputePLL_old(pll, freq, chosen_dot_clock_freq,
- chosen_feedback_div, chosen_frac_feedback_div,
- chosen_reference_div, chosen_post_div, flags);
+ switch (radeon_crtc->pll_algo) {
+ case RADEON_PLL_OLD:
+ RADEONComputePLL_old(pll, freq, chosen_dot_clock_freq,
+ chosen_feedback_div, chosen_frac_feedback_div,
+ chosen_reference_div, chosen_post_div, flags);
+ break;
+ case RADEON_PLL_NEW:
+ /* disable frac fb dividers */
+ flags &= ~RADEON_PLL_USE_FRAC_FB_DIV;
+ RADEONComputePLL_new(pll, freq, chosen_dot_clock_freq,
+ chosen_feedback_div, chosen_frac_feedback_div,
+ chosen_reference_div, chosen_post_div, flags);
+ break;
}
}
diff --git a/src/radeon_probe.h b/src/radeon_probe.h
index dc02bdf..cab077f 100644
--- a/src/radeon_probe.h
+++ b/src/radeon_probe.h
@@ -147,6 +147,11 @@ typedef struct
Bool hw_capable;
} RADEONI2CBusRec, *RADEONI2CBusPtr;
+enum radeon_pll_algo {
+ RADEON_PLL_OLD,
+ RADEON_PLL_NEW
+};
+
typedef struct _RADEONCrtcPrivateRec {
void *crtc_rotate_mem;
void *cursor_mem;
@@ -164,6 +169,7 @@ typedef struct _RADEONCrtcPrivateRec {
float vsc;
float hsc;
int pll_id;
+ enum radeon_pll_algo pll_algo;
} RADEONCrtcPrivateRec, *RADEONCrtcPrivatePtr;
typedef struct _radeon_encoder {
commit c1b817c45477c21234abaaebe78feb7ea4fd92b1
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Mon Apr 12 16:32:04 2010 -0400
atom: disable TV encoder when VGA is in use
Switching between TV and VGA caused problems on some
systems since the TV encoder was left enabled.
Should fix fdo bug 25520.
diff --git a/src/atombios_output.c b/src/atombios_output.c
index 0a54657..3e2d301 100644
--- a/src/atombios_output.c
+++ b/src/atombios_output.c
@@ -1801,8 +1801,12 @@ atombios_output_mode_set(xf86OutputPtr output,
case ENCODER_OBJECT_ID_INTERNAL_DAC2:
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
atombios_output_dac_setup(output, ATOM_ENABLE);
- if (radeon_output->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
- atombios_output_tv_setup(output, ATOM_ENABLE);
+ if (radeon_output->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
+ if (radeon_output->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
+ atombios_output_tv_setup(output, ATOM_ENABLE);
+ else
+ atombios_output_tv_setup(output, ATOM_DISABLE);
+ }
break;
}
atombios_apply_output_quirks(output, adjusted_mode);
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