xf86-video-intel: 4 commits - src/i830_batchbuffer.h src/i830_driver.c src/i830_render.c src/i830_uxa.c src/i915_render.c
Daniel Vetter
danvet at kemper.freedesktop.org
Tue Apr 13 00:18:30 PDT 2010
src/i830_batchbuffer.h | 25 ++++++++++++++++++-------
src/i830_driver.c | 5 +++--
src/i830_render.c | 36 ++++++++++++++++++++++++++++++------
src/i830_uxa.c | 18 +++++++++---------
src/i915_render.c | 24 ++++++++++++++++++++----
5 files changed, 80 insertions(+), 28 deletions(-)
New commits:
commit 324a2810da3fbae35637ba9080f31f9383db0868
Author: Daniel Vetter <daniel.vetter at ffwll.ch>
Date: Tue Apr 13 08:39:43 2010 +0200
i830 render: check aperture space requirements
No point not doing this.
Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
diff --git a/src/i830_render.c b/src/i830_render.c
index 5e524b3..8e559c9 100644
--- a/src/i830_render.c
+++ b/src/i830_render.c
@@ -438,6 +438,12 @@ i830_prepare_composite(int op, PicturePtr source_picture,
{
ScrnInfoPtr scrn = xf86Screens[dest_picture->pDrawable->pScreen->myNum];
intel_screen_private *intel = intel_get_screen_private(scrn);
+ drm_intel_bo *bo_table[] = {
+ NULL, /* batch_bo */
+ i830_get_pixmap_bo(source),
+ mask ? i830_get_pixmap_bo(mask) : NULL,
+ i830_get_pixmap_bo(dest),
+ };
intel->render_source_picture = source_picture;
intel->render_source = source;
@@ -458,6 +464,9 @@ i830_prepare_composite(int op, PicturePtr source_picture,
if (!i830_get_dest_format(dest_picture, &intel->render_dest_format))
return FALSE;
+ if (!i830_get_aperture_space(scrn, bo_table, ARRAY_SIZE(bo_table)))
+ return FALSE;
+
if (mask) {
intel->transform[1] = NULL;
intel->scale_units[1][0] = -1;
commit 804263c10df2fedb2f0debab6cdfaa6a89184a42
Author: Daniel Vetter <daniel.vetter at ffwll.ch>
Date: Sun Apr 11 12:56:24 2010 +0200
render: tell the kernel explicitly when fences are needed
This slighlty improves xrender performance on fence reg starved
i8xx hw.
I've also changed a few function calls to the new names from the
compat ones while looking at the code.
The i915 textured video path is not converted because atm the xv
code does not use tiled surfaces.
Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
diff --git a/src/i830_batchbuffer.h b/src/i830_batchbuffer.h
index 1fc273b..2793bc0 100644
--- a/src/i830_batchbuffer.h
+++ b/src/i830_batchbuffer.h
@@ -98,13 +98,21 @@ static inline void
intel_batch_emit_reloc(intel_screen_private *intel,
dri_bo * bo,
uint32_t read_domains,
- uint32_t write_domains, uint32_t delta)
+ uint32_t write_domains, uint32_t delta, int needs_fence)
{
assert(intel_batch_space(intel) >= 4);
*(uint32_t *) (intel->batch_ptr + intel->batch_used) =
bo->offset + delta;
- dri_bo_emit_reloc(intel->batch_bo, read_domains, write_domains, delta,
- intel->batch_used, bo);
+ if (needs_fence)
+ drm_intel_bo_emit_reloc_fence(intel->batch_bo,
+ intel->batch_used,
+ bo, delta,
+ read_domains, write_domains);
+ else
+ drm_intel_bo_emit_reloc(intel->batch_bo, intel->batch_used,
+ bo, delta,
+ read_domains, write_domains);
+
intel->batch_used += 4;
}
@@ -132,7 +140,7 @@ intel_batch_mark_pixmap_domains(intel_screen_private *intel,
static inline void
intel_batch_emit_reloc_pixmap(intel_screen_private *intel, PixmapPtr pixmap,
uint32_t read_domains, uint32_t write_domain,
- uint32_t delta)
+ uint32_t delta, int needs_fence)
{
struct intel_pixmap *priv = i830_get_pixmap_intel(pixmap);
@@ -143,17 +151,20 @@ intel_batch_emit_reloc_pixmap(intel_screen_private *intel, PixmapPtr pixmap,
intel_batch_emit_reloc(intel, priv->bo,
read_domains, write_domain,
- delta);
+ delta, needs_fence);
}
#define ALIGN_BATCH(align) intel_batch_align(intel, align);
#define OUT_BATCH(dword) intel_batch_emit_dword(intel, dword)
#define OUT_RELOC(bo, read_domains, write_domains, delta) \
- intel_batch_emit_reloc (intel, bo, read_domains, write_domains, delta)
+ intel_batch_emit_reloc(intel, bo, read_domains, write_domains, delta, 0)
#define OUT_RELOC_PIXMAP(pixmap, reads, write, delta) \
- intel_batch_emit_reloc_pixmap(intel, pixmap, reads, write, delta)
+ intel_batch_emit_reloc_pixmap(intel, pixmap, reads, write, delta, 0)
+
+#define OUT_RELOC_PIXMAP_FENCED(pixmap, reads, write, delta) \
+ intel_batch_emit_reloc_pixmap(intel, pixmap, reads, write, delta, 1)
union intfloat {
float f;
diff --git a/src/i830_driver.c b/src/i830_driver.c
index 40ad9c3..d0ce552 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -1048,8 +1048,9 @@ void i830_init_bufmgr(ScrnInfoPtr scrn)
if (IS_I865G(intel))
batch_size = 4096;
- intel->bufmgr = intel_bufmgr_gem_init(intel->drmSubFD, batch_size);
- intel_bufmgr_gem_enable_reuse(intel->bufmgr);
+ intel->bufmgr = drm_intel_bufmgr_gem_init(intel->drmSubFD, batch_size);
+ drm_intel_bufmgr_gem_enable_reuse(intel->bufmgr);
+ drm_intel_bufmgr_gem_enable_fenced_relocs(intel->bufmgr);
list_init(&intel->batch_pixmaps);
list_init(&intel->flush_pixmaps);
diff --git a/src/i830_uxa.c b/src/i830_uxa.c
index 589e16d..09c2ef3 100644
--- a/src/i830_uxa.c
+++ b/src/i830_uxa.c
@@ -295,8 +295,8 @@ static void i830_uxa_solid(PixmapPtr pixmap, int x1, int y1, int x2, int y2)
OUT_BATCH(intel->BR[13] | pitch);
OUT_BATCH((y1 << 16) | (x1 & 0xffff));
OUT_BATCH((y2 << 16) | (x2 & 0xffff));
- OUT_RELOC_PIXMAP(pixmap, I915_GEM_DOMAIN_RENDER,
- I915_GEM_DOMAIN_RENDER, 0);
+ OUT_RELOC_PIXMAP_FENCED(pixmap, I915_GEM_DOMAIN_RENDER,
+ I915_GEM_DOMAIN_RENDER, 0);
OUT_BATCH(intel->BR[16]);
ADVANCE_BATCH();
}
@@ -411,15 +411,15 @@ i830_uxa_copy(PixmapPtr dest, int src_x1, int src_y1, int dst_x1,
OUT_BATCH(intel->BR[13] | dst_pitch);
OUT_BATCH((dst_y1 << 16) | (dst_x1 & 0xffff));
OUT_BATCH((dst_y2 << 16) | (dst_x2 & 0xffff));
- OUT_RELOC_PIXMAP(dest,
- I915_GEM_DOMAIN_RENDER,
- I915_GEM_DOMAIN_RENDER,
- 0);
+ OUT_RELOC_PIXMAP_FENCED(dest,
+ I915_GEM_DOMAIN_RENDER,
+ I915_GEM_DOMAIN_RENDER,
+ 0);
OUT_BATCH((src_y1 << 16) | (src_x1 & 0xffff));
OUT_BATCH(src_pitch);
- OUT_RELOC_PIXMAP(intel->render_source,
- I915_GEM_DOMAIN_RENDER, 0,
- 0);
+ OUT_RELOC_PIXMAP_FENCED(intel->render_source,
+ I915_GEM_DOMAIN_RENDER, 0,
+ 0);
ADVANCE_BATCH();
}
commit a619a7831228dc52f0fef7d92c92f701e5aeaa94
Author: Daniel Vetter <daniel.vetter at ffwll.ch>
Date: Thu Apr 8 18:49:01 2010 +0200
i915 render: use tiling bits where possible
This is in preparation to explicit fence allocation with execbuf2.
Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
diff --git a/src/i915_render.c b/src/i915_render.c
index 819b963..98b5b88 100644
--- a/src/i915_render.c
+++ b/src/i915_render.c
@@ -275,7 +275,7 @@ static Bool i915_texture_setup(PicturePtr picture, PixmapPtr pixmap, int unit)
intel_screen_private *intel = intel_get_screen_private(scrn);
uint32_t format, pitch, filter;
int w, h, i;
- uint32_t wrap_mode;
+ uint32_t wrap_mode, tiling_bits;
pitch = intel_get_pixmap_pitch(pixmap);
w = picture->pDrawable->width;
@@ -328,10 +328,18 @@ static Bool i915_texture_setup(PicturePtr picture, PixmapPtr pixmap, int unit)
}
/* offset filled in at emit time */
+ if (i830_pixmap_tiled(pixmap)) {
+ tiling_bits = MS3_TILED_SURFACE;
+ if (i830_get_pixmap_intel(pixmap)->tiling
+ == I915_TILING_Y)
+ tiling_bits |= MS3_TILE_WALK;
+ } else
+ tiling_bits = 0;
+
intel->texture[unit] = pixmap;
intel->mapstate[unit * 3 + 0] = 0;
intel->mapstate[unit * 3 + 1] = format |
- MS3_USE_FENCE_REGS |
+ tiling_bits |
((pixmap->drawable.height - 1) << MS3_HEIGHT_SHIFT) |
((pixmap->drawable.width - 1) << MS3_WIDTH_SHIFT);
intel->mapstate[unit * 3 + 2] = ((pitch / 4) - 1) << MS4_PITCH_SHIFT;
@@ -482,7 +490,7 @@ static void i915_emit_composite_setup(ScrnInfoPtr scrn)
PixmapPtr mask = intel->render_mask;
PixmapPtr dest = intel->render_dest;
uint32_t dst_format = intel->i915_render_state.dst_format, dst_pitch;
- uint32_t blendctl;
+ uint32_t blendctl, tiling_bits;
Bool is_affine_src, is_affine_mask;
Bool is_solid_src, is_solid_mask;
int tex_count, t;
@@ -540,8 +548,16 @@ static void i915_emit_composite_setup(ScrnInfoPtr scrn)
OUT_BATCH (intel->render_mask_solid);
}
+ if (i830_pixmap_tiled(dest)) {
+ tiling_bits = BUF_3D_TILED_SURFACE;
+ if (i830_get_pixmap_intel(dest)->tiling
+ == I915_TILING_Y)
+ tiling_bits |= BUF_3D_TILE_WALK_Y;
+ } else
+ tiling_bits = 0;
+
OUT_BATCH(_3DSTATE_BUF_INFO_CMD);
- OUT_BATCH(BUF_3D_ID_COLOR_BACK | BUF_3D_USE_FENCE |
+ OUT_BATCH(BUF_3D_ID_COLOR_BACK | tiling_bits |
BUF_3D_PITCH(dst_pitch));
OUT_RELOC_PIXMAP(dest, I915_GEM_DOMAIN_RENDER,
I915_GEM_DOMAIN_RENDER, 0);
commit 55cd36046e61e8d51b5cb754a81cdb54e3eab166
Author: Daniel Vetter <daniel.vetter at ffwll.ch>
Date: Thu Apr 8 14:48:35 2010 +0200
i830 render: use tiling bits where possible
This is in preparation to explicit fence allocation with execbuf2.
Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
diff --git a/src/i830_render.c b/src/i830_render.c
index 71296d2..5e524b3 100644
--- a/src/i830_render.c
+++ b/src/i830_render.c
@@ -283,7 +283,7 @@ static void i830_texture_setup(PicturePtr picture, PixmapPtr pixmap, int unit)
ScrnInfoPtr scrn = xf86Screens[picture->pDrawable->pScreen->myNum];
intel_screen_private *intel = intel_get_screen_private(scrn);
- uint32_t format, pitch, filter;
+ uint32_t format, tiling_bits, pitch, filter;
uint32_t wrap_mode;
uint32_t texcoordtype;
@@ -338,16 +338,23 @@ static void i830_texture_setup(PicturePtr picture, PixmapPtr pixmap, int unit)
else
format |= MAPSURF_32BIT;
+ if (i830_pixmap_tiled(pixmap)) {
+ tiling_bits = TM0S1_TILED_SURFACE;
+ if (i830_get_pixmap_intel(pixmap)->tiling
+ == I915_TILING_Y)
+ tiling_bits |= TM0S1_TILE_WALK;
+ } else
+ tiling_bits = 0;
+
ATOMIC_BATCH(10);
OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_2 |
LOAD_TEXTURE_MAP(unit) | 4);
- OUT_RELOC_PIXMAP(pixmap, I915_GEM_DOMAIN_SAMPLER, 0,
- TM0S0_USE_FENCE);
+ OUT_RELOC_PIXMAP(pixmap, I915_GEM_DOMAIN_SAMPLER, 0, 0);
OUT_BATCH(((pixmap->drawable.height -
1) << TM0S1_HEIGHT_SHIFT) | ((pixmap->drawable.width -
1) <<
TM0S1_WIDTH_SHIFT) |
- format);
+ format | tiling_bits);
OUT_BATCH((pitch / 4 - 1) << TM0S2_PITCH_SHIFT | TM0S2_MAP_2D);
OUT_BATCH(filter);
OUT_BATCH(0); /* default color */
@@ -535,7 +542,7 @@ i830_prepare_composite(int op, PicturePtr source_picture,
static void i830_emit_composite_state(ScrnInfoPtr scrn)
{
intel_screen_private *intel = intel_get_screen_private(scrn);
- uint32_t vf2;
+ uint32_t vf2, tiling_bits;
uint32_t texcoordfmt = 0;
intel->needs_render_state_emit = FALSE;
@@ -545,8 +552,16 @@ static void i830_emit_composite_state(ScrnInfoPtr scrn)
ATOMIC_BATCH(21);
+ if (i830_pixmap_tiled(intel->render_dest)) {
+ tiling_bits = BUF_3D_TILED_SURFACE;
+ if (i830_get_pixmap_intel(intel->render_dest)->tiling
+ == I915_TILING_Y)
+ tiling_bits |= BUF_3D_TILE_WALK_Y;
+ } else
+ tiling_bits = 0;
+
OUT_BATCH(_3DSTATE_BUF_INFO_CMD);
- OUT_BATCH(BUF_3D_ID_COLOR_BACK | BUF_3D_USE_FENCE |
+ OUT_BATCH(BUF_3D_ID_COLOR_BACK | tiling_bits |
BUF_3D_PITCH(intel_get_pixmap_pitch(intel->render_dest)));
OUT_RELOC_PIXMAP(intel->render_dest,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
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