[ANNOUNCE] xf86-video-intel 2.20.3

Chris Wilson chris at chris-wilson.co.uk
Sat Aug 4 01:40:37 PDT 2012

Just a minor bugfix for gen4 chipsets (965gm, gm45 and friends) that
crept into 2.20.2. As an added bonus, the pessimistic workaround for a
GPU hang on gen4 has been relaxed and the shaders have been overhauled
which should pave the way to eliminating the last of the uncommon CPU
operations, along with immediately realising a small perforamnce

Bugs fixed since 2.20.2:

 * Update DPMS bookkeeping after modeset

 * Avoid overlapping gpu/cpu damage after ignoring cpu damage in the
   consideration of placement for the operation.

 * Enable acceleration by default on 830gm/845g. The GMCH on this pair
   of chipsets is notoriously incoherent, so the GPU is almost certainly
   going to hang at some point, though unlikely to hang the system and
   should automatically disable acceleration (and thence behave
   identically as if the acceleration was disabled from the start).
   Option "NoAccel" can be used to disable all 2D acceleration and
   Option "DRI" can be used to disable all 3D acceleration.

 * Fix vertex bookkeeping for gen4 that was causing corruption in the
   command stream.

Chris Wilson (41):
      sna/gen4: Further refinement to the GT allocation
      sna/gen4: Move the common vertex_offset==0 check into the flush()
      sna: Honour the Option "DRI"
      Don't disable acceleration on 830/845g by default
      sna: Disable the warning for a hung GPU is we manually set wedged
      sna: Assert that we never attempt to submit a batch whilst wedged
      sna: Debug option to test migration of inactive pixmaps
      sna: Prefer not to create a GPU bo without RENDER acceleration
      sna: Add the brw assembler
      sna: Assemble SF and WM kernels using brw
      sna/gen4: Compile basic kernels at runtime
      sna/gen5: Compile basic kernels at runtime
      sna/gen6: Compile basic kernels at runtime
      sna/gen7: Compile basic kernels at runtime
      sna/gen7: Prefer the BLT for self-copies
      sna: Export sna_drawable_use_bo() to select target for FillRectangles
      sna: Avoid overlapping gpu/cpu damage with IGNORE_CPU
      sna: Be more careful with damage reduction during CompositeRectangles
      sna: Update DPMS mode on CRTC after forcing the outputs on
      sna/gen4: Tidy debugging code
      sna: Generate shaders for SNB+ 8-pixel dispatch
      sna/gen7: Enable 8 pixel dispatch
      sna/gen6: Enable 8 pixel dispatch
      sna/gen4+: Implement an opacity shader
      sna/gen6+: Reduce floats-per-vertex for spans
      sna/gen4: Flush not required between fill vertices, only nomaskcomposite
      sna/gen7: Only force a stall for a dirty target if also used as a blend source
      sna/gen7: Simplify the force-stall detection
      Revert "sna/gen7: Prefer the BLT for self-copies"
      sna/gen6: Install a fallback 16-pixel shader
      sna: Fix computation of st values for SIMD8 dispatch
      sna: Add validation of the clear flag to pixmap debugging
      sna/gen7: Prefer the BLT for self-copies
      sna: Ensure we only mark a clear for a fill on the GPU bo
      sna: Drop the clear flag as we discard the GPU damage
      sna: Limit the batch size on all gen7 variants
      sna/gen7: Add constant variations and hookup a basic GT descriptor for Haswell
      Unexport intel_chipsets
      Pass the chipset info through driverPrivate rather than a global pointer
      sna/gen7: Correct number of texture coordinates used for video
      2.20.3 release

Gwenole Beauchesne (6):
      Introduce a chipset identifier for Haswell (Ivybridge successor)
      uxa: add IS_HSW() macro to distinguish Haswell from Ivybridge
      uxa: use at least 64 URB entries for Haswell
      uxa: fix max PS threads shift value for Haswell
      uxa: set "Shader Channel Select" fields in surface state for Haswell
      uxa: fix 3DSTATE_PS to fill in number of samples for Haswell

Zhigang Gong (1):
      uxa/dri (glamor): Use exchange buffer in glamor fixup.

git tag: 2.20.3

MD5:  10c317605f49631bc24697d392ef68d9  xf86-video-intel-2.20.3.tar.bz2
SHA1: e1a74655f97a595e0edad9bc892b34c9bf3e2cc3  xf86-video-intel-2.20.3.tar.bz2
SHA256: effca1382e595cc071b109818150db229ffb54f92769e4758398abbe69acb92c  xf86-video-intel-2.20.3.tar.bz2

MD5:  6a8b2f168647701c1c54dd8c1c1ff643  xf86-video-intel-2.20.3.tar.gz
SHA1: b7cda16fbe52163279f14057e6895bfe6ece7ea8  xf86-video-intel-2.20.3.tar.gz
SHA256: 8ff35d99c76c42c726d3b7ba9b843a1d658e287db6a722b9603f34a21500b6f4  xf86-video-intel-2.20.3.tar.gz

Chris Wilson, Intel Open Source Technology Centre
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